Microchip Technology Inc. ATSAM3X4E 2024.06.03 Atmel ATSAM3X4E Microcontroller CM3 r2p0 selectable true 4 false 8 32 ADC Analog-to-Digital Converter ADC 0x0 0x0 0x50 registers n ADC 37 ACR Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL ADC Bias Current Control 8 2 read-write TSON Temperature Sensor On 4 1 read-write CDR0 Channel Data Register 0x50 32 read-only n DATA Converted Data 0 12 read-only CDR1 Channel Data Register 0x54 32 read-only n DATA Converted Data 0 12 read-only CDR10 Channel Data Register 0x78 32 read-only n DATA Converted Data 0 12 read-only CDR11 Channel Data Register 0x7C 32 read-only n DATA Converted Data 0 12 read-only CDR12 Channel Data Register 0x80 32 read-only n DATA Converted Data 0 12 read-only CDR13 Channel Data Register 0x84 32 read-only n DATA Converted Data 0 12 read-only CDR14 Channel Data Register 0x88 32 read-only n DATA Converted Data 0 12 read-only CDR15 Channel Data Register 0x8C 32 read-only n DATA Converted Data 0 12 read-only CDR2 Channel Data Register 0x58 32 read-only n DATA Converted Data 0 12 read-only CDR3 Channel Data Register 0x5C 32 read-only n DATA Converted Data 0 12 read-only CDR4 Channel Data Register 0x60 32 read-only n DATA Converted Data 0 12 read-only CDR5 Channel Data Register 0x64 32 read-only n DATA Converted Data 0 12 read-only CDR6 Channel Data Register 0x68 32 read-only n DATA Converted Data 0 12 read-only CDR7 Channel Data Register 0x6C 32 read-only n DATA Converted Data 0 12 read-only CDR8 Channel Data Register 0x70 32 read-only n DATA Converted Data 0 12 read-only CDR9 Channel Data Register 0x74 32 read-only n DATA Converted Data 0 12 read-only CDR[0] Channel Data Register 0xA0 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[10] Channel Data Register 0x49C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[11] Channel Data Register 0x518 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[12] Channel Data Register 0x598 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[13] Channel Data Register 0x61C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[14] Channel Data Register 0x6A4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[15] Channel Data Register 0x730 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[1] Channel Data Register 0xF4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[2] Channel Data Register 0x14C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[3] Channel Data Register 0x1A8 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[4] Channel Data Register 0x208 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[5] Channel Data Register 0x26C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[6] Channel Data Register 0x2D4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[7] Channel Data Register 0x340 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[8] Channel Data Register 0x3B0 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[9] Channel Data Register 0x424 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CGR Channel Gain Register 0x48 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 read-write GAIN1 Gain for Channel 1 2 2 read-write GAIN10 Gain for Channel 10 20 2 read-write GAIN11 Gain for Channel 11 22 2 read-write GAIN12 Gain for Channel 12 24 2 read-write GAIN13 Gain for Channel 13 26 2 read-write GAIN14 Gain for Channel 14 28 2 read-write GAIN15 Gain for Channel 15 30 2 read-write GAIN2 Gain for Channel 2 4 2 read-write GAIN3 Gain for Channel 3 6 2 read-write GAIN4 Gain for Channel 4 8 2 read-write GAIN5 Gain for Channel 5 10 2 read-write GAIN6 Gain for Channel 6 12 2 read-write GAIN7 Gain for Channel 7 14 2 read-write GAIN8 Gain for Channel 8 16 2 read-write GAIN9 Gain for Channel 9 18 2 read-write CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH10 Channel 10 Disable 10 1 write-only CH11 Channel 11 Disable 11 1 write-only CH12 Channel 12 Disable 12 1 write-only CH13 Channel 13 Disable 13 1 write-only CH14 Channel 14 Disable 14 1 write-only CH15 Channel 15 Disable 15 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CH8 Channel 8 Disable 8 1 write-only CH9 Channel 9 Disable 9 1 write-only CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH10 Channel 10 Enable 10 1 write-only CH11 Channel 11 Enable 11 1 write-only CH12 Channel 12 Enable 12 1 write-only CH13 Channel 13 Enable 13 1 write-only CH14 Channel 14 Enable 14 1 write-only CH15 Channel 15 Enable 15 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CH8 Channel 8 Enable 8 1 write-only CH9 Channel 9 Enable 9 1 write-only CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH10 Channel 10 Status 10 1 read-only CH11 Channel 11 Status 11 1 read-only CH12 Channel 12 Status 12 1 read-only CH13 Channel 13 Status 13 1 read-only CH14 Channel 14 Status 14 1 read-only CH15 Channel 15 Status 15 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only CH8 Channel 8 Status 8 1 read-only CH9 Channel 9 Status 9 1 read-only COR Channel Offset Register 0x4C 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 16 1 read-write DIFF1 Differential inputs for channel 1 17 1 read-write DIFF10 Differential inputs for channel 10 26 1 read-write DIFF11 Differential inputs for channel 11 27 1 read-write DIFF12 Differential inputs for channel 12 28 1 read-write DIFF13 Differential inputs for channel 13 29 1 read-write DIFF14 Differential inputs for channel 14 30 1 read-write DIFF15 Differential inputs for channel 15 31 1 read-write DIFF2 Differential inputs for channel 2 18 1 read-write DIFF3 Differential inputs for channel 3 19 1 read-write DIFF4 Differential inputs for channel 4 20 1 read-write DIFF5 Differential inputs for channel 5 21 1 read-write DIFF6 Differential inputs for channel 6 22 1 read-write DIFF7 Differential inputs for channel 7 23 1 read-write DIFF8 Differential inputs for channel 8 24 1 read-write DIFF9 Differential inputs for channel 9 25 1 read-write OFF0 Offset for channel 0 0 1 read-write OFF1 Offset for channel 1 1 1 read-write OFF10 Offset for channel 10 10 1 read-write OFF11 Offset for channel 11 11 1 read-write OFF12 Offset for channel 12 12 1 read-write OFF13 Offset for channel 13 13 1 read-write OFF14 Offset for channel 14 14 1 read-write OFF15 Offset for channel 15 15 1 read-write OFF2 Offset for channel 2 2 1 read-write OFF3 Offset for channel 3 3 1 read-write OFF4 Offset for channel 4 4 1 read-write OFF5 Offset for channel 5 5 1 read-write OFF6 Offset for channel 6 6 1 read-write OFF7 Offset for channel 7 7 1 read-write OFF8 Offset for channel 8 8 1 read-write OFF9 Offset for channel 9 9 1 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 write-only SWRST Software Reset 0 1 write-only CWR Compare Window Register 0x44 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 12 read-write LOWTHRES Low Threshold 0 12 read-write EMR Extended Mode Register 0x40 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write CMPMODE Comparison Mode 0 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 4 4 read-write TAG TAG of the ADC_LDCR register 24 1 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only ENDRX End of Receive Buffer Interrupt Disable 27 1 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC10 End of Conversion Interrupt Disable 10 10 1 write-only EOC11 End of Conversion Interrupt Disable 11 11 1 write-only EOC12 End of Conversion Interrupt Disable 12 12 1 write-only EOC13 End of Conversion Interrupt Disable 13 13 1 write-only EOC14 End of Conversion Interrupt Disable 14 14 1 write-only EOC15 End of Conversion Interrupt Disable 15 15 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only EOC8 End of Conversion Interrupt Disable 8 8 1 write-only EOC9 End of Conversion Interrupt Disable 9 9 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 28 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only ENDRX End of Receive Buffer Interrupt Enable 27 1 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC10 End of Conversion Interrupt Enable 10 10 1 write-only EOC11 End of Conversion Interrupt Enable 11 11 1 write-only EOC12 End of Conversion Interrupt Enable 12 12 1 write-only EOC13 End of Conversion Interrupt Enable 13 13 1 write-only EOC14 End of Conversion Interrupt Enable 14 14 1 write-only EOC15 End of Conversion Interrupt Enable 15 15 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only EOC8 End of Conversion Interrupt Enable 8 8 1 write-only EOC9 End of Conversion Interrupt Enable 9 9 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 28 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only ENDRX End of Receive Buffer Interrupt Mask 27 1 read-only EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC10 End of Conversion Interrupt Mask 10 10 1 read-only EOC11 End of Conversion Interrupt Mask 11 11 1 read-only EOC12 End of Conversion Interrupt Mask 12 12 1 read-only EOC13 End of Conversion Interrupt Mask 13 13 1 read-only EOC14 End of Conversion Interrupt Mask 14 14 1 read-only EOC15 End of Conversion Interrupt Mask 15 15 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only EOC8 End of Conversion Interrupt Mask 8 8 1 read-only EOC9 End of Conversion Interrupt Mask 9 9 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 28 1 read-only ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error 26 1 read-only DRDY Data Ready 24 1 read-only ENDRX End of RX Buffer 27 1 read-only EOC0 End of Conversion 0 0 1 read-only EOC1 End of Conversion 1 1 1 read-only EOC10 End of Conversion 10 10 1 read-only EOC11 End of Conversion 11 11 1 read-only EOC12 End of Conversion 12 12 1 read-only EOC13 End of Conversion 13 13 1 read-only EOC14 End of Conversion 14 14 1 read-only EOC15 End of Conversion 15 15 1 read-only EOC2 End of Conversion 2 2 1 read-only EOC3 End of Conversion 3 3 1 read-only EOC4 End of Conversion 4 4 1 read-only EOC5 End of Conversion 5 5 1 read-only EOC6 End of Conversion 6 6 1 read-only EOC7 End of Conversion 7 7 1 read-only EOC8 End of Conversion 8 8 1 read-only EOC9 End of Conversion 9 9 1 read-only GOVRE General Overrun Error 25 1 read-only RXBUFF RX Buffer Full 28 1 read-only LCDR Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 12 4 read-only LDATA Last Data Converted 0 12 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 ANACH Analog Change 23 1 read-write NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 0 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers 1 FREERUN Free Run Mode 7 1 read-write OFF Normal Mode 0 ON Free Run Mode: Never wait for any trigger. 1 FWUP Fast Wake Up 6 1 read-write OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions 0 ON If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF 1 PRESCAL Prescaler Rate Selection 8 8 read-write SETTLING Analog Settling Time 20 2 read-write AST3 3 periods of ADCClock 0x0 AST5 5 periods of ADCClock 0x1 AST9 9 periods of ADCClock 0x2 AST17 17 periods of ADCClock 0x3 SLEEP Sleep Mode 5 1 read-write NORMAL Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions 0 SLEEP Sleep Mode: The wake-up time can be modified by programming FWUP bit 1 STARTUP Start Up Time 16 4 read-write SUT0 0 periods of ADCClock 0x0 SUT8 8 periods of ADCClock 0x1 SUT16 16 periods of ADCClock 0x2 SUT24 24 periods of ADCClock 0x3 SUT64 64 periods of ADCClock 0x4 SUT80 80 periods of ADCClock 0x5 SUT96 96 periods of ADCClock 0x6 SUT112 112 periods of ADCClock 0x7 SUT512 512 periods of ADCClock 0x8 SUT576 576 periods of ADCClock 0x9 SUT640 640 periods of ADCClock 0xA SUT704 704 periods of ADCClock 0xB SUT768 768 periods of ADCClock 0xC SUT832 832 periods of ADCClock 0xD SUT896 896 periods of ADCClock 0xE SUT960 960 periods of ADCClock 0xF TRACKTIM Tracking Time 24 4 read-write TRANSFER Transfer Period 28 2 read-write TRGEN Trigger Enable 0 1 read-write DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 read-write ADC_TRIG0 External : ADCTRG 0x0 ADC_TRIG1 TIOA Output of the Timer Counter Channel 0 0x1 ADC_TRIG2 TIOA Output of the Timer Counter Channel 1 0x2 ADC_TRIG3 TIOA Output of the Timer Counter Channel 2 0x3 ADC_TRIG4 PWM Event Line 0 0x4 ADC_TRIG5 PWM Event Line 0 0x5 USEQ Use Sequence Enable 31 1 read-write NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 0 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. 1 OVER Overrun Status Register 0x3C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE10 Overrun Error 10 10 1 read-only OVRE11 Overrun Error 11 11 1 read-only OVRE12 Overrun Error 12 12 1 read-only OVRE13 Overrun Error 13 13 1 read-only OVRE14 Overrun Error 14 14 1 read-only OVRE15 Overrun Error 15 15 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only OVRE5 Overrun Error 5 5 1 read-only OVRE6 Overrun Error 6 6 1 read-only OVRE7 Overrun Error 7 7 1 read-only OVRE8 Overrun Error 8 8 1 read-only OVRE9 Overrun Error 9 9 1 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SEQR1 Channel Sequence Register 1 0x8 32 read-write n 0x0 0x0 USCH1 User Sequence Number 1 0 4 read-write USCH2 User Sequence Number 2 4 4 read-write USCH3 User Sequence Number 3 8 4 read-write USCH4 User Sequence Number 4 12 4 read-write USCH5 User Sequence Number 5 16 4 read-write USCH6 User Sequence Number 6 20 4 read-write USCH7 User Sequence Number 7 24 4 read-write USCH8 User Sequence Number 8 28 4 read-write SEQR2 Channel Sequence Register 2 0xC 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 4 4 read-write USCH11 User Sequence Number 11 8 4 read-write USCH12 User Sequence Number 12 12 4 read-write USCH13 User Sequence Number 13 16 4 read-write USCH14 User Sequence Number 14 20 4 read-write USCH15 User Sequence Number 15 24 4 read-write USCH9 User Sequence Number 9 0 4 read-write WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x414443 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only CAN0 Controller Area Network 0 CAN 0x0 0x0 0x50 registers n CAN0 43 ACR Abort Command Register 0x28 32 write-only n 0x0 0x0 MB0 Abort Request for Mailbox 0 0 1 write-only MB1 Abort Request for Mailbox 1 1 1 write-only MB2 Abort Request for Mailbox 2 2 1 write-only MB3 Abort Request for Mailbox 3 3 1 write-only MB4 Abort Request for Mailbox 4 4 1 write-only MB5 Abort Request for Mailbox 5 5 1 write-only MB6 Abort Request for Mailbox 6 6 1 write-only MB7 Abort Request for Mailbox 7 7 1 write-only BR Baudrate Register 0x14 32 read-write n 0x0 0x0 BRP Baudrate Prescaler. 16 7 read-write PHASE1 Phase 1 segment 4 3 read-write PHASE2 Phase 2 segment 0 3 read-write PROPAG Programming time segment 8 3 read-write SJW Re-synchronization jump width 12 2 read-write SMP Sampling Mode 24 1 read-write ONCE The incoming bit stream is sampled once at sample point. 0 THREE The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. 1 ECR Error Counter Register 0x20 32 read-only n 0x0 0x0 REC Receive Error Counter 0 8 read-only TEC Transmit Error Counter 16 8 read-only IDR Interrupt Disable Register 0x8 32 write-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Disable 26 1 write-only BERR Bit Error Interrupt Disable 28 1 write-only BOFF Bus Off Mode Interrupt Disable 19 1 write-only CERR CRC Error Interrupt Disable 24 1 write-only ERRA Error Active Mode Interrupt Disable 16 1 write-only ERRP Error Passive Mode Interrupt Disable 18 1 write-only FERR Form Error Interrupt Disable 27 1 write-only MB0 Mailbox 0 Interrupt Disable 0 1 write-only MB1 Mailbox 1 Interrupt Disable 1 1 write-only MB2 Mailbox 2 Interrupt Disable 2 1 write-only MB3 Mailbox 3 Interrupt Disable 3 1 write-only MB4 Mailbox 4 Interrupt Disable 4 1 write-only MB5 Mailbox 5 Interrupt Disable 5 1 write-only MB6 Mailbox 6 Interrupt Disable 6 1 write-only MB7 Mailbox 7 Interrupt Disable 7 1 write-only SERR Stuffing Error Interrupt Disable 25 1 write-only SLEEP Sleep Interrupt Disable 20 1 write-only TOVF Timer Overflow Interrupt 22 1 write-only TSTP TimeStamp Interrupt Disable 23 1 write-only WAKEUP Wakeup Interrupt Disable 21 1 write-only WARN Warning Limit Interrupt Disable 17 1 write-only IER Interrupt Enable Register 0x4 32 write-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Enable 26 1 write-only BERR Bit Error Interrupt Enable 28 1 write-only BOFF Bus Off Mode Interrupt Enable 19 1 write-only CERR CRC Error Interrupt Enable 24 1 write-only ERRA Error Active Mode Interrupt Enable 16 1 write-only ERRP Error Passive Mode Interrupt Enable 18 1 write-only FERR Form Error Interrupt Enable 27 1 write-only MB0 Mailbox 0 Interrupt Enable 0 1 write-only MB1 Mailbox 1 Interrupt Enable 1 1 write-only MB2 Mailbox 2 Interrupt Enable 2 1 write-only MB3 Mailbox 3 Interrupt Enable 3 1 write-only MB4 Mailbox 4 Interrupt Enable 4 1 write-only MB5 Mailbox 5 Interrupt Enable 5 1 write-only MB6 Mailbox 6 Interrupt Enable 6 1 write-only MB7 Mailbox 7 Interrupt Enable 7 1 write-only SERR Stuffing Error Interrupt Enable 25 1 write-only SLEEP Sleep Interrupt Enable 20 1 write-only TOVF Timer Overflow Interrupt Enable 22 1 write-only TSTP TimeStamp Interrupt Enable 23 1 write-only WAKEUP Wakeup Interrupt Enable 21 1 write-only WARN Warning Limit Interrupt Enable 17 1 write-only IMR Interrupt Mask Register 0xC 32 read-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Mask 26 1 read-only BERR Bit Error Interrupt Mask 28 1 read-only BOFF Bus Off Mode Interrupt Mask 19 1 read-only CERR CRC Error Interrupt Mask 24 1 read-only ERRA Error Active Mode Interrupt Mask 16 1 read-only ERRP Error Passive Mode Interrupt Mask 18 1 read-only FERR Form Error Interrupt Mask 27 1 read-only MB0 Mailbox 0 Interrupt Mask 0 1 read-only MB1 Mailbox 1 Interrupt Mask 1 1 read-only MB2 Mailbox 2 Interrupt Mask 2 1 read-only MB3 Mailbox 3 Interrupt Mask 3 1 read-only MB4 Mailbox 4 Interrupt Mask 4 1 read-only MB5 Mailbox 5 Interrupt Mask 5 1 read-only MB6 Mailbox 6 Interrupt Mask 6 1 read-only MB7 Mailbox 7 Interrupt Mask 7 1 read-only SERR Stuffing Error Interrupt Mask 25 1 read-only SLEEP Sleep Interrupt Mask 20 1 read-only TOVF Timer Overflow Interrupt Mask 22 1 read-only TSTP Timestamp Interrupt Mask 23 1 read-only WAKEUP Wakeup Interrupt Mask 21 1 read-only WARN Warning Limit Interrupt Mask 17 1 read-only MAM0 Mailbox Acceptance Mask Register (MB = 0) 0x204 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM1 Mailbox Acceptance Mask Register (MB = 1) 0x224 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM2 Mailbox Acceptance Mask Register (MB = 2) 0x244 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM3 Mailbox Acceptance Mask Register (MB = 3) 0x264 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM4 Mailbox Acceptance Mask Register (MB = 4) 0x284 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM5 Mailbox Acceptance Mask Register (MB = 5) 0x2A4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM6 Mailbox Acceptance Mask Register (MB = 6) 0x2C4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM7 Mailbox Acceptance Mask Register (MB = 7) 0x2E4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MCR0 Mailbox Control Register (MB = 0) 0x21C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR1 Mailbox Control Register (MB = 1) 0x23C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR2 Mailbox Control Register (MB = 2) 0x25C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR3 Mailbox Control Register (MB = 3) 0x27C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR4 Mailbox Control Register (MB = 4) 0x29C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR5 Mailbox Control Register (MB = 5) 0x2BC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR6 Mailbox Control Register (MB = 6) 0x2DC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR7 Mailbox Control Register (MB = 7) 0x2FC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MDH0 Mailbox Data High Register (MB = 0) 0x218 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH1 Mailbox Data High Register (MB = 1) 0x238 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH2 Mailbox Data High Register (MB = 2) 0x258 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH3 Mailbox Data High Register (MB = 3) 0x278 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH4 Mailbox Data High Register (MB = 4) 0x298 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH5 Mailbox Data High Register (MB = 5) 0x2B8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH6 Mailbox Data High Register (MB = 6) 0x2D8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH7 Mailbox Data High Register (MB = 7) 0x2F8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDL0 Mailbox Data Low Register (MB = 0) 0x214 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL1 Mailbox Data Low Register (MB = 1) 0x234 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL2 Mailbox Data Low Register (MB = 2) 0x254 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL3 Mailbox Data Low Register (MB = 3) 0x274 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL4 Mailbox Data Low Register (MB = 4) 0x294 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL5 Mailbox Data Low Register (MB = 5) 0x2B4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL6 Mailbox Data Low Register (MB = 6) 0x2D4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL7 Mailbox Data Low Register (MB = 7) 0x2F4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MFID0 Mailbox Family ID Register (MB = 0) 0x20C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID1 Mailbox Family ID Register (MB = 1) 0x22C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID2 Mailbox Family ID Register (MB = 2) 0x24C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID3 Mailbox Family ID Register (MB = 3) 0x26C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID4 Mailbox Family ID Register (MB = 4) 0x28C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID5 Mailbox Family ID Register (MB = 5) 0x2AC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID6 Mailbox Family ID Register (MB = 6) 0x2CC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID7 Mailbox Family ID Register (MB = 7) 0x2EC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MID0 Mailbox ID Register (MB = 0) 0x208 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID1 Mailbox ID Register (MB = 1) 0x228 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID2 Mailbox ID Register (MB = 2) 0x248 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID3 Mailbox ID Register (MB = 3) 0x268 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID4 Mailbox ID Register (MB = 4) 0x288 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID5 Mailbox ID Register (MB = 5) 0x2A8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID6 Mailbox ID Register (MB = 6) 0x2C8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID7 Mailbox ID Register (MB = 7) 0x2E8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MMR0 Mailbox Mode Register (MB = 0) 0x200 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR1 Mailbox Mode Register (MB = 1) 0x220 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR2 Mailbox Mode Register (MB = 2) 0x240 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR3 Mailbox Mode Register (MB = 3) 0x260 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR4 Mailbox Mode Register (MB = 4) 0x280 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR5 Mailbox Mode Register (MB = 5) 0x2A0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR6 Mailbox Mode Register (MB = 6) 0x2C0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR7 Mailbox Mode Register (MB = 7) 0x2E0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MR Mode Register 0x0 32 read-write n 0x0 0x0 ABM Disable/Enable Autobaud/Listen mode 2 1 read-write CANEN CAN Controller Enable 0 1 read-write DRPT Disable Repeat 7 1 read-write LPM Disable/Enable Low Power Mode 1 1 read-write OVL Disable/Enable Overload Frame 3 1 read-write RXSYNC Reception Synchronization Stage (not readable) 24 3 read-write DOUBLE_PP Rx Signal with Double Synchro Stages (2 Positive Edges) 0x0 DOUBLE_PN Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) 0x1 SINGLE_P Rx Signal with Single Synchro Stage (Positive Edge) 0x2 NONE Rx Signal with No Synchro Stage 0x3 TEOF Timestamp messages at each end of Frame 4 1 read-write TIMFRZ Enable Timer Freeze 6 1 read-write TTM Disable/Enable Time Triggered Mode 5 1 read-write MSR0 Mailbox Status Register (MB = 0) 0x210 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR1 Mailbox Status Register (MB = 1) 0x230 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR2 Mailbox Status Register (MB = 2) 0x250 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR3 Mailbox Status Register (MB = 3) 0x270 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR4 Mailbox Status Register (MB = 4) 0x290 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR5 Mailbox Status Register (MB = 5) 0x2B0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR6 Mailbox Status Register (MB = 6) 0x2D0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR7 Mailbox Status Register (MB = 7) 0x2F0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 AERR Acknowledgment Error 26 1 read-only BERR Bit Error 28 1 read-only BOFF Bus Off Mode 19 1 read-only CERR Mailbox CRC Error 24 1 read-only ERRA Error Active Mode 16 1 read-only ERRP Error Passive Mode 18 1 read-only FERR Form Error 27 1 read-only MB0 Mailbox 0 Event 0 1 read-only MB1 Mailbox 1 Event 1 1 read-only MB2 Mailbox 2 Event 2 1 read-only MB3 Mailbox 3 Event 3 1 read-only MB4 Mailbox 4 Event 4 1 read-only MB5 Mailbox 5 Event 5 1 read-only MB6 Mailbox 6 Event 6 1 read-only MB7 Mailbox 7 Event 7 1 read-only OVLSY Overload busy 31 1 read-only RBSY Receiver busy 29 1 read-only SERR Mailbox Stuffing Error 25 1 read-only SLEEP CAN controller in Low power Mode 20 1 read-only TBSY Transmitter busy 30 1 read-only TOVF Timer Overflow 22 1 read-only TSTP 23 1 read-only WAKEUP CAN controller is not in Low power Mode 21 1 read-only WARN Warning Limit 17 1 read-only TCR Transfer Command Register 0x24 32 write-only n 0x0 0x0 MB0 Transfer Request for Mailbox 0 0 1 write-only MB1 Transfer Request for Mailbox 1 1 1 write-only MB2 Transfer Request for Mailbox 2 2 1 write-only MB3 Transfer Request for Mailbox 3 3 1 write-only MB4 Transfer Request for Mailbox 4 4 1 write-only MB5 Transfer Request for Mailbox 5 5 1 write-only MB6 Transfer Request for Mailbox 6 6 1 write-only MB7 Transfer Request for Mailbox 7 7 1 write-only TIMRST Timer Reset 31 1 write-only TIM Timer Register 0x18 32 read-only n 0x0 0x0 TIMER Timer 0 16 read-only TIMESTP Timestamp Register 0x1C 32 read-only n 0x0 0x0 MTIMESTAMP Timestamp 0 16 read-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY SPI Write Protection Key Password 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only CAN1 Controller Area Network 1 CAN 0x0 0x0 0x50 registers n CAN1 44 ACR Abort Command Register 0x28 32 write-only n 0x0 0x0 MB0 Abort Request for Mailbox 0 0 1 write-only MB1 Abort Request for Mailbox 1 1 1 write-only MB2 Abort Request for Mailbox 2 2 1 write-only MB3 Abort Request for Mailbox 3 3 1 write-only MB4 Abort Request for Mailbox 4 4 1 write-only MB5 Abort Request for Mailbox 5 5 1 write-only MB6 Abort Request for Mailbox 6 6 1 write-only MB7 Abort Request for Mailbox 7 7 1 write-only BR Baudrate Register 0x14 32 read-write n 0x0 0x0 BRP Baudrate Prescaler. 16 7 read-write PHASE1 Phase 1 segment 4 3 read-write PHASE2 Phase 2 segment 0 3 read-write PROPAG Programming time segment 8 3 read-write SJW Re-synchronization jump width 12 2 read-write SMP Sampling Mode 24 1 read-write ONCE The incoming bit stream is sampled once at sample point. 0 THREE The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. 1 ECR Error Counter Register 0x20 32 read-only n 0x0 0x0 REC Receive Error Counter 0 8 read-only TEC Transmit Error Counter 16 8 read-only IDR Interrupt Disable Register 0x8 32 write-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Disable 26 1 write-only BERR Bit Error Interrupt Disable 28 1 write-only BOFF Bus Off Mode Interrupt Disable 19 1 write-only CERR CRC Error Interrupt Disable 24 1 write-only ERRA Error Active Mode Interrupt Disable 16 1 write-only ERRP Error Passive Mode Interrupt Disable 18 1 write-only FERR Form Error Interrupt Disable 27 1 write-only MB0 Mailbox 0 Interrupt Disable 0 1 write-only MB1 Mailbox 1 Interrupt Disable 1 1 write-only MB2 Mailbox 2 Interrupt Disable 2 1 write-only MB3 Mailbox 3 Interrupt Disable 3 1 write-only MB4 Mailbox 4 Interrupt Disable 4 1 write-only MB5 Mailbox 5 Interrupt Disable 5 1 write-only MB6 Mailbox 6 Interrupt Disable 6 1 write-only MB7 Mailbox 7 Interrupt Disable 7 1 write-only SERR Stuffing Error Interrupt Disable 25 1 write-only SLEEP Sleep Interrupt Disable 20 1 write-only TOVF Timer Overflow Interrupt 22 1 write-only TSTP TimeStamp Interrupt Disable 23 1 write-only WAKEUP Wakeup Interrupt Disable 21 1 write-only WARN Warning Limit Interrupt Disable 17 1 write-only IER Interrupt Enable Register 0x4 32 write-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Enable 26 1 write-only BERR Bit Error Interrupt Enable 28 1 write-only BOFF Bus Off Mode Interrupt Enable 19 1 write-only CERR CRC Error Interrupt Enable 24 1 write-only ERRA Error Active Mode Interrupt Enable 16 1 write-only ERRP Error Passive Mode Interrupt Enable 18 1 write-only FERR Form Error Interrupt Enable 27 1 write-only MB0 Mailbox 0 Interrupt Enable 0 1 write-only MB1 Mailbox 1 Interrupt Enable 1 1 write-only MB2 Mailbox 2 Interrupt Enable 2 1 write-only MB3 Mailbox 3 Interrupt Enable 3 1 write-only MB4 Mailbox 4 Interrupt Enable 4 1 write-only MB5 Mailbox 5 Interrupt Enable 5 1 write-only MB6 Mailbox 6 Interrupt Enable 6 1 write-only MB7 Mailbox 7 Interrupt Enable 7 1 write-only SERR Stuffing Error Interrupt Enable 25 1 write-only SLEEP Sleep Interrupt Enable 20 1 write-only TOVF Timer Overflow Interrupt Enable 22 1 write-only TSTP TimeStamp Interrupt Enable 23 1 write-only WAKEUP Wakeup Interrupt Enable 21 1 write-only WARN Warning Limit Interrupt Enable 17 1 write-only IMR Interrupt Mask Register 0xC 32 read-only n 0x0 0x0 AERR Acknowledgment Error Interrupt Mask 26 1 read-only BERR Bit Error Interrupt Mask 28 1 read-only BOFF Bus Off Mode Interrupt Mask 19 1 read-only CERR CRC Error Interrupt Mask 24 1 read-only ERRA Error Active Mode Interrupt Mask 16 1 read-only ERRP Error Passive Mode Interrupt Mask 18 1 read-only FERR Form Error Interrupt Mask 27 1 read-only MB0 Mailbox 0 Interrupt Mask 0 1 read-only MB1 Mailbox 1 Interrupt Mask 1 1 read-only MB2 Mailbox 2 Interrupt Mask 2 1 read-only MB3 Mailbox 3 Interrupt Mask 3 1 read-only MB4 Mailbox 4 Interrupt Mask 4 1 read-only MB5 Mailbox 5 Interrupt Mask 5 1 read-only MB6 Mailbox 6 Interrupt Mask 6 1 read-only MB7 Mailbox 7 Interrupt Mask 7 1 read-only SERR Stuffing Error Interrupt Mask 25 1 read-only SLEEP Sleep Interrupt Mask 20 1 read-only TOVF Timer Overflow Interrupt Mask 22 1 read-only TSTP Timestamp Interrupt Mask 23 1 read-only WAKEUP Wakeup Interrupt Mask 21 1 read-only WARN Warning Limit Interrupt Mask 17 1 read-only MAM0 Mailbox Acceptance Mask Register (MB = 0) 0x204 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM1 Mailbox Acceptance Mask Register (MB = 1) 0x224 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM2 Mailbox Acceptance Mask Register (MB = 2) 0x244 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM3 Mailbox Acceptance Mask Register (MB = 3) 0x264 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM4 Mailbox Acceptance Mask Register (MB = 4) 0x284 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM5 Mailbox Acceptance Mask Register (MB = 5) 0x2A4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM6 Mailbox Acceptance Mask Register (MB = 6) 0x2C4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MAM7 Mailbox Acceptance Mask Register (MB = 7) 0x2E4 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MCR0 Mailbox Control Register (MB = 0) 0x21C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR1 Mailbox Control Register (MB = 1) 0x23C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR2 Mailbox Control Register (MB = 2) 0x25C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR3 Mailbox Control Register (MB = 3) 0x27C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR4 Mailbox Control Register (MB = 4) 0x29C 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR5 Mailbox Control Register (MB = 5) 0x2BC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR6 Mailbox Control Register (MB = 6) 0x2DC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MCR7 Mailbox Control Register (MB = 7) 0x2FC 32 write-only n 0x0 0x0 MACR Abort Request for Mailbox x 22 1 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MDH0 Mailbox Data High Register (MB = 0) 0x218 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH1 Mailbox Data High Register (MB = 1) 0x238 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH2 Mailbox Data High Register (MB = 2) 0x258 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH3 Mailbox Data High Register (MB = 3) 0x278 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH4 Mailbox Data High Register (MB = 4) 0x298 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH5 Mailbox Data High Register (MB = 5) 0x2B8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH6 Mailbox Data High Register (MB = 6) 0x2D8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDH7 Mailbox Data High Register (MB = 7) 0x2F8 32 read-write n 0x0 0x0 MDH Message Data High Value 0 32 read-write MDL0 Mailbox Data Low Register (MB = 0) 0x214 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL1 Mailbox Data Low Register (MB = 1) 0x234 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL2 Mailbox Data Low Register (MB = 2) 0x254 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL3 Mailbox Data Low Register (MB = 3) 0x274 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL4 Mailbox Data Low Register (MB = 4) 0x294 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL5 Mailbox Data Low Register (MB = 5) 0x2B4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL6 Mailbox Data Low Register (MB = 6) 0x2D4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MDL7 Mailbox Data Low Register (MB = 7) 0x2F4 32 read-write n 0x0 0x0 MDL Message Data Low Value 0 32 read-write MFID0 Mailbox Family ID Register (MB = 0) 0x20C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID1 Mailbox Family ID Register (MB = 1) 0x22C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID2 Mailbox Family ID Register (MB = 2) 0x24C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID3 Mailbox Family ID Register (MB = 3) 0x26C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID4 Mailbox Family ID Register (MB = 4) 0x28C 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID5 Mailbox Family ID Register (MB = 5) 0x2AC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID6 Mailbox Family ID Register (MB = 6) 0x2CC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MFID7 Mailbox Family ID Register (MB = 7) 0x2EC 32 read-only n 0x0 0x0 MFID Family ID 0 29 read-only MID0 Mailbox ID Register (MB = 0) 0x208 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID1 Mailbox ID Register (MB = 1) 0x228 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID2 Mailbox ID Register (MB = 2) 0x248 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID3 Mailbox ID Register (MB = 3) 0x268 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID4 Mailbox ID Register (MB = 4) 0x288 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID5 Mailbox ID Register (MB = 5) 0x2A8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID6 Mailbox ID Register (MB = 6) 0x2C8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MID7 Mailbox ID Register (MB = 7) 0x2E8 32 read-write n 0x0 0x0 MIDE Identifier Version 29 1 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MMR0 Mailbox Mode Register (MB = 0) 0x200 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR1 Mailbox Mode Register (MB = 1) 0x220 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR2 Mailbox Mode Register (MB = 2) 0x240 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR3 Mailbox Mode Register (MB = 3) 0x260 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR4 Mailbox Mode Register (MB = 4) 0x280 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR5 Mailbox Mode Register (MB = 5) 0x2A0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR6 Mailbox Mode Register (MB = 6) 0x2C0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MMR7 Mailbox Mode Register (MB = 7) 0x2E0 32 read-write n 0x0 0x0 MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MR Mode Register 0x0 32 read-write n 0x0 0x0 ABM Disable/Enable Autobaud/Listen mode 2 1 read-write CANEN CAN Controller Enable 0 1 read-write DRPT Disable Repeat 7 1 read-write LPM Disable/Enable Low Power Mode 1 1 read-write OVL Disable/Enable Overload Frame 3 1 read-write RXSYNC Reception Synchronization Stage (not readable) 24 3 read-write DOUBLE_PP Rx Signal with Double Synchro Stages (2 Positive Edges) 0x0 DOUBLE_PN Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) 0x1 SINGLE_P Rx Signal with Single Synchro Stage (Positive Edge) 0x2 NONE Rx Signal with No Synchro Stage 0x3 TEOF Timestamp messages at each end of Frame 4 1 read-write TIMFRZ Enable Timer Freeze 6 1 read-write TTM Disable/Enable Time Triggered Mode 5 1 read-write MSR0 Mailbox Status Register (MB = 0) 0x210 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR1 Mailbox Status Register (MB = 1) 0x230 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR2 Mailbox Status Register (MB = 2) 0x250 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR3 Mailbox Status Register (MB = 3) 0x270 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR4 Mailbox Status Register (MB = 4) 0x290 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR5 Mailbox Status Register (MB = 5) 0x2B0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR6 Mailbox Status Register (MB = 6) 0x2D0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only MSR7 Mailbox Status Register (MB = 7) 0x2F0 32 read-only n 0x0 0x0 MABT Mailbox Message Abort 22 1 read-only MDLC Mailbox Data Length Code 16 4 read-only MMI Mailbox Message Ignored 24 1 read-only MRDY Mailbox Ready 23 1 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MTIMESTAMP Timer value 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 AERR Acknowledgment Error 26 1 read-only BERR Bit Error 28 1 read-only BOFF Bus Off Mode 19 1 read-only CERR Mailbox CRC Error 24 1 read-only ERRA Error Active Mode 16 1 read-only ERRP Error Passive Mode 18 1 read-only FERR Form Error 27 1 read-only MB0 Mailbox 0 Event 0 1 read-only MB1 Mailbox 1 Event 1 1 read-only MB2 Mailbox 2 Event 2 1 read-only MB3 Mailbox 3 Event 3 1 read-only MB4 Mailbox 4 Event 4 1 read-only MB5 Mailbox 5 Event 5 1 read-only MB6 Mailbox 6 Event 6 1 read-only MB7 Mailbox 7 Event 7 1 read-only OVLSY Overload busy 31 1 read-only RBSY Receiver busy 29 1 read-only SERR Mailbox Stuffing Error 25 1 read-only SLEEP CAN controller in Low power Mode 20 1 read-only TBSY Transmitter busy 30 1 read-only TOVF Timer Overflow 22 1 read-only TSTP 23 1 read-only WAKEUP CAN controller is not in Low power Mode 21 1 read-only WARN Warning Limit 17 1 read-only TCR Transfer Command Register 0x24 32 write-only n 0x0 0x0 MB0 Transfer Request for Mailbox 0 0 1 write-only MB1 Transfer Request for Mailbox 1 1 1 write-only MB2 Transfer Request for Mailbox 2 2 1 write-only MB3 Transfer Request for Mailbox 3 3 1 write-only MB4 Transfer Request for Mailbox 4 4 1 write-only MB5 Transfer Request for Mailbox 5 5 1 write-only MB6 Transfer Request for Mailbox 6 6 1 write-only MB7 Transfer Request for Mailbox 7 7 1 write-only TIMRST Timer Reset 31 1 write-only TIM Timer Register 0x18 32 read-only n 0x0 0x0 TIMER Timer 0 16 read-only TIMESTP Timestamp Register 0x1C 32 read-only n 0x0 0x0 MTIMESTAMP Timestamp 0 16 read-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY SPI Write Protection Key Password 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only CHIPID Chip Identifier CHIPID 0x0 0x0 0x200 registers n CIDR Chip ID Register 0x0 32 read-only n 0x0 0x0 ARCH Architecture Identifier 20 8 read-only SAM3AxC SAM3AxC (100-pin version) 0x83 SAM3XxC SAM3XxC (100-pin version) 0x84 SAM3XxE SAM3XxE (144-pin version) 0x85 SAM3XxG SAM3XxG (208/217-pin version) 0x86 EPROC Embedded Processor 5 3 read-only ARM946ES ARM946ES 0x1 ARM7TDMI ARM7TDMI 0x2 CM3 Cortex-M3 0x3 ARM920T ARM920T 0x4 ARM926EJS ARM926EJS 0x5 CA5 Cortex-A5 0x6 CM4 Cortex-M4 0x7 EXT Extension Flag 31 1 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPTYP Nonvolatile Program Memory Type 28 3 read-only ROM ROM 0x0 ROMLESS ROMless or on-chip Flash 0x1 FLASH Embedded Flash Memory 0x2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 0x3 SRAM SRAM emulating ROM 0x4 SRAMSIZ Internal SRAM Size 16 4 read-only 48K 48 Kbytes 0x0 192K 192 Kbytes 0x1 2K 2 Kbytes 0x2 6K 6 Kbytes 0x3 24K 24 Kbytes 0x4 4K 4 Kbytes 0x5 80K 80 Kbytes 0x6 160K 160 Kbytes 0x7 8K 8 Kbytes 0x8 16K 16 Kbytes 0x9 32K 32 Kbytes 0xA 64K 64 Kbytes 0xB 128K 128 Kbytes 0xC 256K 256 Kbytes 0xD 96K 96 Kbytes 0xE 512K 512 Kbytes 0xF VERSION Version of the Device 0 5 read-only EXID Chip ID Extension Register 0x4 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 read-only DACC Digital-to-Analog Converter Controller DACC 0x0 0x0 0x50 registers n DACC 38 ACR Analog Current Register 0x94 32 read-write n 0x0 0x0 IBCTLCH0 Analog Output Current Control 0 2 read-write IBCTLCH1 Analog Output Current Control 2 2 read-write IBCTLDACCORE Bias Current Control for DAC Core 8 2 read-write CDR Conversion Data Register 0x20 32 write-only n 0x0 0x0 DATA Data to Convert 0 32 write-only CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 write-only IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ENDTX End of Transmit Buffer Interrupt Disable 2 1 write-only EOC End of Conversion Interrupt Disable 1 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 3 1 write-only TXRDY Transmit Ready Interrupt Disable. 0 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ENDTX End of Transmit Buffer Interrupt Enable 2 1 write-only EOC End of Conversion Interrupt Enable 1 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 3 1 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ENDTX End of Transmit Buffer Interrupt Mask 2 1 read-only EOC End of Conversion Interrupt Mask 1 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 3 1 read-only TXRDY Transmit Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 ENDTX End of DMA Interrupt Flag 2 1 read-only EOC End of Conversion Interrupt Flag 1 1 read-only TXBUFE Transmit Buffer Empty 3 1 read-only TXRDY Transmit Ready Interrupt Flag 0 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 FASTWKUP Fast Wake up Mode 6 1 read-write MAXS Max Speed Mode 21 1 read-write NORMAL Normal Mode 0 MAXIMUM Max Speed Mode enabled 1 REFRESH Refresh Period 8 8 read-write SLEEP Sleep Mode 5 1 read-write STARTUP Startup Time Selection 24 6 read-write 0 0 periods of DACClock 0x0 8 8 periods of DACClock 0x1 1024 1024 periods of DACClock 0x10 1088 1088 periods of DACClock 0x11 1152 1152 periods of DACClock 0x12 1216 1216 periods of DACClock 0x13 1280 1280 periods of DACClock 0x14 1344 1344 periods of DACClock 0x15 1408 1408 periods of DACClock 0x16 1472 1472 periods of DACClock 0x17 1536 1536 periods of DACClock 0x18 1600 1600 periods of DACClock 0x19 1664 1664 periods of DACClock 0x1A 1728 1728 periods of DACClock 0x1B 1792 1792 periods of DACClock 0x1C 1856 1856 periods of DACClock 0x1D 1920 1920 periods of DACClock 0x1E 1984 1984 periods of DACClock 0x1F 16 16 periods of DACClock 0x2 24 24 periods of DACClock 0x3 64 64 periods of DACClock 0x4 80 80 periods of DACClock 0x5 96 96 periods of DACClock 0x6 112 112 periods of DACClock 0x7 512 512 periods of DACClock 0x8 576 576 periods of DACClock 0x9 640 640 periods of DACClock 0xA 704 704 periods of DACClock 0xB 768 768 periods of DACClock 0xC 832 832 periods of DACClock 0xD 896 896 periods of DACClock 0xE 960 960 periods of DACClock 0xF TAG Tag Selection Mode 20 1 read-write DIS Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. 0 EN Tag selection mode enabled 1 TRGEN Trigger Enable 0 1 read-write DIS External trigger mode disabled. DACC in free running mode. 0 EN External trigger mode enabled. 1 TRGSEL Trigger Selection 1 3 read-write USER_SEL User Channel Selection 16 2 read-write CHANNEL0 Channel 0 0 CHANNEL1 Channel 1 1 WORD Word Transfer 4 1 read-write HALF Half-Word transfer 0 WORD Word Transfer 1 PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPMR Write Protect Mode register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status register 0xE8 32 read-only n 0x0 0x0 WPROTADDR Write protection error address 8 8 read-only WPROTERR Write protection error 0 1 read-only DMAC DMA Controller DMAC 0x0 0x0 0x50 registers n DMAC 39 CFG0 DMAC Channel Configuration Register (ch_num = 0) 0x50 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CFG1 DMAC Channel Configuration Register (ch_num = 1) 0x78 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CFG2 DMAC Channel Configuration Register (ch_num = 2) 0xA0 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CFG3 DMAC Channel Configuration Register (ch_num = 3) 0xC8 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CFG4 DMAC Channel Configuration Register (ch_num = 4) 0xF0 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CFG5 DMAC Channel Configuration Register (ch_num = 5) 0x118 32 read-write n 0x0 0x0 AHB_PROT AHB Protection 24 3 read-write DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_PER Destination with Peripheral identifier 4 4 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SRC_PER Source with Peripheral identifier 0 4 read-write CHDR DMAC Channel Handler Disable Register 0x2C 32 write-only n 0x0 0x0 DIS0 Disable [5:0] 0 1 write-only DIS1 Disable [5:0] 1 1 write-only DIS2 Disable [5:0] 2 1 write-only DIS3 Disable [5:0] 3 1 write-only DIS4 Disable [5:0] 4 1 write-only DIS5 Disable [5:0] 5 1 write-only RES0 Resume [5:0] 8 1 write-only RES1 Resume [5:0] 9 1 write-only RES2 Resume [5:0] 10 1 write-only RES3 Resume [5:0] 11 1 write-only RES4 Resume [5:0] 12 1 write-only RES5 Resume [5:0] 13 1 write-only CHER DMAC Channel Handler Enable Register 0x28 32 write-only n 0x0 0x0 ENA0 Enable [5:0] 0 1 write-only ENA1 Enable [5:0] 1 1 write-only ENA2 Enable [5:0] 2 1 write-only ENA3 Enable [5:0] 3 1 write-only ENA4 Enable [5:0] 4 1 write-only ENA5 Enable [5:0] 5 1 write-only KEEP0 Keep on [5:0] 24 1 write-only KEEP1 Keep on [5:0] 25 1 write-only KEEP2 Keep on [5:0] 26 1 write-only KEEP3 Keep on [5:0] 27 1 write-only KEEP4 Keep on [5:0] 28 1 write-only KEEP5 Keep on [5:0] 29 1 write-only SUSP0 Suspend [5:0] 8 1 write-only SUSP1 Suspend [5:0] 9 1 write-only SUSP2 Suspend [5:0] 10 1 write-only SUSP3 Suspend [5:0] 11 1 write-only SUSP4 Suspend [5:0] 12 1 write-only SUSP5 Suspend [5:0] 13 1 write-only CHSR DMAC Channel Handler Status Register 0x30 32 read-only n 0x0 0x0 EMPT0 Empty [5:0] 16 1 read-only EMPT1 Empty [5:0] 17 1 read-only EMPT2 Empty [5:0] 18 1 read-only EMPT3 Empty [5:0] 19 1 read-only EMPT4 Empty [5:0] 20 1 read-only EMPT5 Empty [5:0] 21 1 read-only ENA0 Enable [5:0] 0 1 read-only ENA1 Enable [5:0] 1 1 read-only ENA2 Enable [5:0] 2 1 read-only ENA3 Enable [5:0] 3 1 read-only ENA4 Enable [5:0] 4 1 read-only ENA5 Enable [5:0] 5 1 read-only STAL0 Stalled [5:0] 24 1 read-only STAL1 Stalled [5:0] 25 1 read-only STAL2 Stalled [5:0] 26 1 read-only STAL3 Stalled [5:0] 27 1 read-only STAL4 Stalled [5:0] 28 1 read-only STAL5 Stalled [5:0] 29 1 read-only SUSP0 Suspend [5:0] 8 1 read-only SUSP1 Suspend [5:0] 9 1 read-only SUSP2 Suspend [5:0] 10 1 read-only SUSP3 Suspend [5:0] 11 1 read-only SUSP4 Suspend [5:0] 12 1 read-only SUSP5 Suspend [5:0] 13 1 read-only CREQ DMAC Software Chunk Transfer Request Register 0xC 32 read-write n 0x0 0x0 DCREQ0 Destination Chunk Request 1 1 read-write DCREQ1 Destination Chunk Request 3 1 read-write DCREQ2 Destination Chunk Request 5 1 read-write DCREQ3 Destination Chunk Request 7 1 read-write DCREQ4 Destination Chunk Request 9 1 read-write DCREQ5 Destination Chunk Request 11 1 read-write SCREQ0 Source Chunk Request 0 1 read-write SCREQ1 Source Chunk Request 2 1 read-write SCREQ2 Source Chunk Request 4 1 read-write SCREQ3 Source Chunk Request 6 1 read-write SCREQ4 Source Chunk Request 8 1 read-write SCREQ5 Source Chunk Request 10 1 read-write CTRLA0 DMAC Channel Control A Register (ch_num = 0) 0x48 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLA1 DMAC Channel Control A Register (ch_num = 1) 0x70 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLA2 DMAC Channel Control A Register (ch_num = 2) 0x98 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLA3 DMAC Channel Control A Register (ch_num = 3) 0xC0 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLA4 DMAC Channel Control A Register (ch_num = 4) 0xE8 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLA5 DMAC Channel Control A Register (ch_num = 5) 0x110 32 read-write n 0x0 0x0 BTSIZE Buffer Transfer Size 0 16 read-write DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 CTRLB0 DMAC Channel Control B Register (ch_num = 0) 0x4C 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 CTRLB1 DMAC Channel Control B Register (ch_num = 1) 0x74 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 CTRLB2 DMAC Channel Control B Register (ch_num = 2) 0x9C 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 CTRLB3 DMAC Channel Control B Register (ch_num = 3) 0xC4 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 CTRLB4 DMAC Channel Control B Register (ch_num = 4) 0xEC 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 CTRLB5 DMAC Channel Control B Register (ch_num = 5) 0x114 32 read-write n 0x0 0x0 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 IEN Interrupt Enable Not 30 1 read-write SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DADDR0 DMAC Channel Destination Address Register (ch_num = 0) 0x40 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DADDR1 DMAC Channel Destination Address Register (ch_num = 1) 0x68 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DADDR2 DMAC Channel Destination Address Register (ch_num = 2) 0x90 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DADDR3 DMAC Channel Destination Address Register (ch_num = 3) 0xB8 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DADDR4 DMAC Channel Destination Address Register (ch_num = 4) 0xE0 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DADDR5 DMAC Channel Destination Address Register (ch_num = 5) 0x108 32 read-write n 0x0 0x0 DADDR Channel x Destination Address 0 32 read-write DSCR0 DMAC Channel Descriptor Address Register (ch_num = 0) 0x44 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write DSCR1 DMAC Channel Descriptor Address Register (ch_num = 1) 0x6C 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write DSCR2 DMAC Channel Descriptor Address Register (ch_num = 2) 0x94 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write DSCR3 DMAC Channel Descriptor Address Register (ch_num = 3) 0xBC 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write DSCR4 DMAC Channel Descriptor Address Register (ch_num = 4) 0xE4 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write DSCR5 DMAC Channel Descriptor Address Register (ch_num = 5) 0x10C 32 read-write n 0x0 0x0 DSCR Buffer Transfer Descriptor Address 2 30 read-write EBCIDR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. 0x1C 32 write-only n 0x0 0x0 BTC0 Buffer Transfer Completed [5:0] 0 1 write-only BTC1 Buffer Transfer Completed [5:0] 1 1 write-only BTC2 Buffer Transfer Completed [5:0] 2 1 write-only BTC3 Buffer Transfer Completed [5:0] 3 1 write-only BTC4 Buffer Transfer Completed [5:0] 4 1 write-only BTC5 Buffer Transfer Completed [5:0] 5 1 write-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 write-only ERR0 Access Error [5:0] 16 1 write-only ERR1 Access Error [5:0] 17 1 write-only ERR2 Access Error [5:0] 18 1 write-only ERR3 Access Error [5:0] 19 1 write-only ERR4 Access Error [5:0] 20 1 write-only ERR5 Access Error [5:0] 21 1 write-only EBCIER DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. 0x18 32 write-only n 0x0 0x0 BTC0 Buffer Transfer Completed [5:0] 0 1 write-only BTC1 Buffer Transfer Completed [5:0] 1 1 write-only BTC2 Buffer Transfer Completed [5:0] 2 1 write-only BTC3 Buffer Transfer Completed [5:0] 3 1 write-only BTC4 Buffer Transfer Completed [5:0] 4 1 write-only BTC5 Buffer Transfer Completed [5:0] 5 1 write-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 write-only ERR0 Access Error [5:0] 16 1 write-only ERR1 Access Error [5:0] 17 1 write-only ERR2 Access Error [5:0] 18 1 write-only ERR3 Access Error [5:0] 19 1 write-only ERR4 Access Error [5:0] 20 1 write-only ERR5 Access Error [5:0] 21 1 write-only EBCIMR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. 0x20 32 read-only n 0x0 0x0 BTC0 Buffer Transfer Completed [5:0] 0 1 read-only BTC1 Buffer Transfer Completed [5:0] 1 1 read-only BTC2 Buffer Transfer Completed [5:0] 2 1 read-only BTC3 Buffer Transfer Completed [5:0] 3 1 read-only BTC4 Buffer Transfer Completed [5:0] 4 1 read-only BTC5 Buffer Transfer Completed [5:0] 5 1 read-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 read-only ERR0 Access Error [5:0] 16 1 read-only ERR1 Access Error [5:0] 17 1 read-only ERR2 Access Error [5:0] 18 1 read-only ERR3 Access Error [5:0] 19 1 read-only ERR4 Access Error [5:0] 20 1 read-only ERR5 Access Error [5:0] 21 1 read-only EBCISR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. 0x24 32 read-only n 0x0 0x0 BTC0 Buffer Transfer Completed [5:0] 0 1 read-only BTC1 Buffer Transfer Completed [5:0] 1 1 read-only BTC2 Buffer Transfer Completed [5:0] 2 1 read-only BTC3 Buffer Transfer Completed [5:0] 3 1 read-only BTC4 Buffer Transfer Completed [5:0] 4 1 read-only BTC5 Buffer Transfer Completed [5:0] 5 1 read-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 read-only ERR0 Access Error [5:0] 16 1 read-only ERR1 Access Error [5:0] 17 1 read-only ERR2 Access Error [5:0] 18 1 read-only ERR3 Access Error [5:0] 19 1 read-only ERR4 Access Error [5:0] 20 1 read-only ERR5 Access Error [5:0] 21 1 read-only EN DMAC Enable Register 0x4 32 read-write n 0x0 0x0 ENABLE General Enable of DMA 0 1 read-write GCFG DMAC Global Configuration Register 0x0 32 read-write n 0x0 0x0 ARB_CFG Arbiter Configuration 4 1 read-write FIXED Fixed priority arbiter (see "Basic Definitions" ) 0 ROUND_ROBIN Modified round robin arbiter. 1 LAST DMAC Software Last Transfer Flag Register 0x10 32 read-write n 0x0 0x0 DLAST0 Destination Last 1 1 read-write DLAST1 Destination Last 3 1 read-write DLAST2 Destination Last 5 1 read-write DLAST3 Destination Last 7 1 read-write DLAST4 Destination Last 9 1 read-write DLAST5 Destination Last 11 1 read-write SLAST0 Source Last 0 1 read-write SLAST1 Source Last 2 1 read-write SLAST2 Source Last 4 1 read-write SLAST3 Source Last 6 1 read-write SLAST4 Source Last 8 1 read-write SLAST5 Source Last 10 1 read-write SADDR0 DMAC Channel Source Address Register (ch_num = 0) 0x3C 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SADDR1 DMAC Channel Source Address Register (ch_num = 1) 0x64 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SADDR2 DMAC Channel Source Address Register (ch_num = 2) 0x8C 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SADDR3 DMAC Channel Source Address Register (ch_num = 3) 0xB4 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SADDR4 DMAC Channel Source Address Register (ch_num = 4) 0xDC 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SADDR5 DMAC Channel Source Address Register (ch_num = 5) 0x104 32 read-write n 0x0 0x0 SADDR Channel x Source Address 0 32 read-write SREQ DMAC Software Single Request Register 0x8 32 read-write n 0x0 0x0 DSREQ0 Destination Request 1 1 read-write DSREQ1 Destination Request 3 1 read-write DSREQ2 Destination Request 5 1 read-write DSREQ3 Destination Request 7 1 read-write DSREQ4 Destination Request 9 1 read-write DSREQ5 Destination Request 11 1 read-write SSREQ0 Source Request 0 1 read-write SSREQ1 Source Request 2 1 read-write SSREQ2 Source Request 4 1 read-write SSREQ3 Source Request 6 1 read-write SSREQ4 Source Request 8 1 read-write SSREQ5 Source Request 10 1 read-write WPMR DMAC Write Protect Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x444D41 WPSR DMAC Write Protect Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only EFC0 Embedded Flash Controller 0 EFC 0x0 0x0 0x200 registers n EFC0 6 FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 write-only FCMD Flash Command 0 8 write-only GETD Get Flash Descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 SLB Set Lock Bit 0x08 CLB Clear Lock Bit 0x09 GLB Get Lock Bit 0x0A SGPB Set GPNVM Bit 0x0B CGPB Clear GPNVM Bit 0x0C GGPB Get GPNVM Bit 0x0D STUI Start Read Unique Identifier 0x0E SPUI Stop Read Unique Identifier 0x0F GCALB Get CALIB Bit 0x10 FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 FAM Flash Access Mode 24 1 read-write FRDY Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 read-only FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status 1 1 read-only FLOCKE Flash Lock Error Status 2 1 read-only FRDY Flash Ready Status 0 1 read-only EFC1 Embedded Flash Controller 1 EFC 0x0 0x0 0x200 registers n EFC1 7 FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 write-only FCMD Flash Command 0 8 write-only GETD Get Flash Descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 SLB Set Lock Bit 0x08 CLB Clear Lock Bit 0x09 GLB Get Lock Bit 0x0A SGPB Set GPNVM Bit 0x0B CGPB Clear GPNVM Bit 0x0C GGPB Get GPNVM Bit 0x0D STUI Start Read Unique Identifier 0x0E SPUI Stop Read Unique Identifier 0x0F GCALB Get CALIB Bit 0x10 FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 FAM Flash Access Mode 24 1 read-write FRDY Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 read-only FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status 1 1 read-only FLOCKE Flash Lock Error Status 2 1 read-only FRDY Flash Ready Status 0 1 read-only EMAC Ethernet MAC 10/100 EMAC 0x0 0x0 0x50 registers n EMAC 42 ALE Alignment Errors Register 0x54 32 read-write n 0x0 0x0 ALE Alignment Errors 0 8 read-write CSE Carrier Sense Errors Register 0x68 32 read-write n 0x0 0x0 CSE Carrier Sense Errors 0 8 read-write DTF Deferred Transmission Frames Register 0x58 32 read-write n 0x0 0x0 DTF Deferred Transmission Frames 0 16 read-write ECOL Excessive Collisions Register 0x60 32 read-write n 0x0 0x0 EXCOL Excessive Collisions 0 8 read-write ELE Excessive Length Errors Register 0x78 32 read-write n 0x0 0x0 EXL Excessive Length Errors 0 8 read-write FCSE Frame Check Sequence Errors Register 0x50 32 read-write n 0x0 0x0 FCSE Frame Check Sequence Errors 0 8 read-write FRO Frames Received Ok Register 0x4C 32 read-write n 0x0 0x0 FROK Frames Received OK 0 24 read-write FTO Frames Transmitted Ok Register 0x40 32 read-write n 0x0 0x0 FTOK Frames Transmitted OK 0 24 read-write HRB Hash Register Bottom [31:0] Register 0x90 32 read-write n 0x0 0x0 ADDR 0 32 read-write HRT Hash Register Top [63:32] Register 0x94 32 read-write n 0x0 0x0 ADDR 0 32 read-write IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 HRESP Hresp not OK 11 1 write-only MFD Management Frame sent 0 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLE Retry Limit Exceeded 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only TXERR 6 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 HRESP Hresp not OK 11 1 write-only MFD Management Frame sent 0 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLE Retry Limit Exceeded 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only TXERR 6 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only IMR Interrupt Mask Register 0x30 32 read-only n 0x0 0x0 HRESP Hresp not OK 11 1 read-only MFD Management Frame sent 0 1 read-only PFR Pause Frame Received 12 1 read-only PTZ Pause Time Zero 13 1 read-only RCOMP Receive Complete 1 1 read-only RLE Retry Limit Exceeded 5 1 read-only ROVR Receive Overrun 10 1 read-only RXUBR Receive Used Bit Read 2 1 read-only TCOMP Transmit Complete 7 1 read-only TUND Ethernet Transmit Buffer Underrun 4 1 read-only TXERR 6 1 read-only TXUBR Transmit Used Bit Read 3 1 read-only ISR Interrupt Status Register 0x24 32 read-write n 0x0 0x0 HRESP Hresp not OK 11 1 read-write MFD Management Frame Done 0 1 read-write PFRE Pause Frame Received 12 1 read-write PTZ Pause Time Zero 13 1 read-write RCOMP Receive Complete 1 1 read-write RLEX Retry Limit Exceeded 5 1 read-write ROVR Receive Overrun 10 1 read-write RXUBR Receive Used Bit Read 2 1 read-write TCOMP Transmit Complete 7 1 read-write TUND Ethernet Transmit Buffer Underrun 4 1 read-write TXERR Transmit Error 6 1 read-write TXUBR Transmit Used Bit Read 3 1 read-write LCOL Late Collisions Register 0x5C 32 read-write n 0x0 0x0 LCOL Late Collisions 0 8 read-write MAN Phy Maintenance Register 0x34 32 read-write n 0x0 0x0 CODE 16 2 read-write DATA 0 16 read-write PHYA PHY Address 23 5 read-write REGA Register Address 18 5 read-write RW Read-write 28 2 read-write SOF Start of frame 30 2 read-write MCF Multiple Collision Frames Register 0x48 32 read-write n 0x0 0x0 MCF Multicollision Frames 0 16 read-write NCFGR Network Configuration Register 0x4 32 read-write n 0x0 0x0 BIG Receive 1536 bytes frames 8 1 read-write CAF Copy All Frames 4 1 read-write CLK MDC clock divider 10 2 read-write MCK_8 MCK divided by 8 (MCK up to 20 MHz). 0x0 MCK_16 MCK divided by 16 (MCK up to 40 MHz). 0x1 MCK_32 MCK divided by 32 (MCK up to 80 MHz). 0x2 MCK_64 MCK divided by 64 (MCK up to 160 MHz). 0x3 DRFCS Discard Receive FCS 17 1 read-write EFRHD 18 1 read-write FD Full Duplex 1 1 read-write IRXFCS Ignore RX FCS 19 1 read-write JFRAME Jumbo Frames 3 1 read-write MTI Multicast Hash Enable 6 1 read-write NBC No Broadcast 5 1 read-write PAE Pause Enable 13 1 read-write RBOF Receive Buffer Offset 14 2 read-write OFFSET_0 No offset from start of receive buffer. 0x0 OFFSET_1 One-byte offset from start of receive buffer. 0x1 OFFSET_2 Two-byte offset from start of receive buffer. 0x2 OFFSET_3 Three-byte offset from start of receive buffer. 0x3 RLCE Receive Length field Checking Enable 16 1 read-write RTY Retry test 12 1 read-write SPD Speed 0 1 read-write UNI Unicast Hash Enable 7 1 read-write NCR Network Control Register 0x0 32 read-write n 0x0 0x0 BP Back pressure 8 1 read-write CLRSTAT Clear statistics registers 5 1 read-write INCSTAT Increment statistics registers 6 1 read-write LB LoopBack 0 1 read-write LLB Loopback local 1 1 read-write MPE Management port enable 4 1 read-write RE Receive enable 2 1 read-write TE Transmit enable 3 1 read-write THALT Transmit halt 10 1 read-write TSTART Start transmission 9 1 read-write WESTAT Write enable for statistics registers 7 1 read-write NSR Network Status Register 0x8 32 read-only n 0x0 0x0 IDLE 2 1 read-only MDIO 1 1 read-only PFR Pause Frames Received Register 0x3C 32 read-write n 0x0 0x0 FROK Pause Frames received OK 0 16 read-write PTR Pause Time Register 0x38 32 read-write n 0x0 0x0 PTIME Pause Time 0 16 read-write RBQP Receive Buffer Queue Pointer Register 0x18 32 read-write n 0x0 0x0 ADDR Receive buffer queue pointer address 2 30 read-write RJA Receive Jabbers Register 0x7C 32 read-write n 0x0 0x0 RJB Receive Jabbers 0 8 read-write RLE Received Length Field Mismatch Register 0x88 32 read-write n 0x0 0x0 RLFM Receive Length Field Mismatch 0 8 read-write ROV Receive Overrun Errors Register 0x70 32 read-write n 0x0 0x0 ROVR Receive Overrun 0 8 read-write RRE Receive Resource Errors Register 0x6C 32 read-write n 0x0 0x0 RRE Receive Resource Errors 0 16 read-write RSE Receive Symbol Errors Register 0x74 32 read-write n 0x0 0x0 RSE Receive Symbol Errors 0 8 read-write RSR Receive Status Register 0x20 32 read-write n 0x0 0x0 BNA Buffer Not Available 0 1 read-write OVR Receive Overrun 2 1 read-write REC Frame Received 1 1 read-write SA1B Specific Address 1 Bottom Register 0x98 32 read-write n 0x0 0x0 ADDR 0 32 read-write SA1T Specific Address 1 Top Register 0x9C 32 read-write n 0x0 0x0 ADDR 0 16 read-write SA2B Specific Address 2 Bottom Register 0xA0 32 read-write n 0x0 0x0 ADDR 0 32 read-write SA2T Specific Address 2 Top Register 0xA4 32 read-write n 0x0 0x0 ADDR 0 16 read-write SA3B Specific Address 3 Bottom Register 0xA8 32 read-write n 0x0 0x0 ADDR 0 32 read-write SA3T Specific Address 3 Top Register 0xAC 32 read-write n 0x0 0x0 ADDR 0 16 read-write SA4B Specific Address 4 Bottom Register 0xB0 32 read-write n 0x0 0x0 ADDR 0 32 read-write SA4T Specific Address 4 Top Register 0xB4 32 read-write n 0x0 0x0 ADDR 0 16 read-write SCF Single Collision Frames Register 0x44 32 read-write n 0x0 0x0 SCF Single Collision Frames 0 16 read-write STE SQE Test Errors Register 0x84 32 read-write n 0x0 0x0 SQER SQE test errors 0 8 read-write TBQP Transmit Buffer Queue Pointer Register 0x1C 32 read-write n 0x0 0x0 ADDR Transmit buffer queue pointer address 2 30 read-write TID Type ID Checking Register 0xB8 32 read-write n 0x0 0x0 TID Type ID checking 0 16 read-write TSR Transmit Status Register 0x14 32 read-write n 0x0 0x0 BEX Buffers exhausted mid frame 4 1 read-write COL Collision Occurred 1 1 read-write COMP Transmit Complete 5 1 read-write RLES Retry Limit exceeded 2 1 read-write TGO Transmit Go 3 1 read-write UBR Used Bit Read 0 1 read-write UND Transmit Underrun 6 1 read-write TUND Transmit Underrun Errors Register 0x64 32 read-write n 0x0 0x0 TUND Transmit Underruns 0 8 read-write USF Undersize Frames Register 0x80 32 read-write n 0x0 0x0 USF Undersize frames 0 8 read-write USRIO User Input/Output Register 0xC0 32 read-write n 0x0 0x0 CLKEN Clock Enable 1 1 read-write RMII Reduce MII 0 1 read-write GPBR General Purpose Backup Registers SYSC 0x0 0x0 0x20 registers n GPBR0 General Purpose Backup Register 0x0 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR1 General Purpose Backup Register 0x4 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR2 General Purpose Backup Register 0x8 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR3 General Purpose Backup Register 0xC 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR4 General Purpose Backup Register 0x10 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR5 General Purpose Backup Register 0x14 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR6 General Purpose Backup Register 0x18 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR7 General Purpose Backup Register 0x1C 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[0] General Purpose Backup Register 0x0 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[1] General Purpose Backup Register 0x4 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[2] General Purpose Backup Register 0xC 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[3] General Purpose Backup Register 0x18 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[4] General Purpose Backup Register 0x28 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[5] General Purpose Backup Register 0x3C 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[6] General Purpose Backup Register 0x54 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[7] General Purpose Backup Register 0x70 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write HSMCI High Speed MultiMedia Card Interface HSMCI 0x0 0x0 0x50 registers n HSMCI 21 ARGR Argument Register 0x10 32 read-write n 0x0 0x0 ARG Command Argument 0 32 read-write BLKR Block Register 0x18 32 read-write n 0x0 0x0 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write BLKLEN Data Block Length 16 16 read-write CFG Configuration Register 0x54 32 read-write n 0x0 0x0 FERRCTRL Flow Error flag reset control mode 4 1 read-write FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write CMDR Command Register 0x14 32 write-only n 0x0 0x0 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge 27 1 write-only CMDNB Command Number 0 6 write-only IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 RSPTYP Response Type 6 2 write-only NORESP No response 0x0 48_BIT 48-bit response 0x1 136_BIT 136-bit response 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD: 74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response: Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation. This command allows the host processor to terminate the boot operation mode. 0x7 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SD Card Single Block 0x0 MULTIPLE MMC/SD Card Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 CR Control Register 0x0 32 write-only n 0x0 0x0 MCIDIS Multi-Media Interface Disable 1 1 write-only MCIEN Multi-Media Interface Enable 0 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only PWSEN Power Save Mode Enable 2 1 write-only SWRST Software Reset 7 1 write-only CSTOR Completion Signal Timeout Register 0x1C 32 read-write n 0x0 0x0 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 DMA DMA Configuration Register 0x50 32 read-write n 0x0 0x0 CHKSIZE DMA Channel Read and Write Chunk Size 4 1 read-write 1 1 data available 0 4 4 data available 1 DMAEN DMA Hardware Handshaking Enable 8 1 read-write OFFSET DMA Write Buffer Offset 0 2 read-write ROPT Read Optimization with padding 12 1 read-write DTOR Data Timeout Register 0x8 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 FIFO0 FIFO Memory Aperture0 0x200 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO1 FIFO Memory Aperture0 0x204 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO10 FIFO Memory Aperture0 0x228 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO100 FIFO Memory Aperture0 0x390 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO101 FIFO Memory Aperture0 0x394 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO102 FIFO Memory Aperture0 0x398 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO103 FIFO Memory Aperture0 0x39C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO104 FIFO Memory Aperture0 0x3A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO105 FIFO Memory Aperture0 0x3A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO106 FIFO Memory Aperture0 0x3A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO107 FIFO Memory Aperture0 0x3AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO108 FIFO Memory Aperture0 0x3B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO109 FIFO Memory Aperture0 0x3B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO11 FIFO Memory Aperture0 0x22C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO110 FIFO Memory Aperture0 0x3B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO111 FIFO Memory Aperture0 0x3BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO112 FIFO Memory Aperture0 0x3C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO113 FIFO Memory Aperture0 0x3C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO114 FIFO Memory Aperture0 0x3C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO115 FIFO Memory Aperture0 0x3CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO116 FIFO Memory Aperture0 0x3D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO117 FIFO Memory Aperture0 0x3D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO118 FIFO Memory Aperture0 0x3D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO119 FIFO Memory Aperture0 0x3DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO12 FIFO Memory Aperture0 0x230 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO120 FIFO Memory Aperture0 0x3E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO121 FIFO Memory Aperture0 0x3E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO122 FIFO Memory Aperture0 0x3E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO123 FIFO Memory Aperture0 0x3EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO124 FIFO Memory Aperture0 0x3F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO125 FIFO Memory Aperture0 0x3F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO126 FIFO Memory Aperture0 0x3F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO127 FIFO Memory Aperture0 0x3FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO128 FIFO Memory Aperture0 0x400 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO129 FIFO Memory Aperture0 0x404 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO13 FIFO Memory Aperture0 0x234 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO130 FIFO Memory Aperture0 0x408 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO131 FIFO Memory Aperture0 0x40C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO132 FIFO Memory Aperture0 0x410 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO133 FIFO Memory Aperture0 0x414 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO134 FIFO Memory Aperture0 0x418 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO135 FIFO Memory Aperture0 0x41C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO136 FIFO Memory Aperture0 0x420 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO137 FIFO Memory Aperture0 0x424 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO138 FIFO Memory Aperture0 0x428 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO139 FIFO Memory Aperture0 0x42C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO14 FIFO Memory Aperture0 0x238 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO140 FIFO Memory Aperture0 0x430 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO141 FIFO Memory Aperture0 0x434 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO142 FIFO Memory Aperture0 0x438 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO143 FIFO Memory Aperture0 0x43C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO144 FIFO Memory Aperture0 0x440 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO145 FIFO Memory Aperture0 0x444 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO146 FIFO Memory Aperture0 0x448 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO147 FIFO Memory Aperture0 0x44C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO148 FIFO Memory Aperture0 0x450 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO149 FIFO Memory Aperture0 0x454 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO15 FIFO Memory Aperture0 0x23C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO150 FIFO Memory Aperture0 0x458 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO151 FIFO Memory Aperture0 0x45C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO152 FIFO Memory Aperture0 0x460 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO153 FIFO Memory Aperture0 0x464 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO154 FIFO Memory Aperture0 0x468 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO155 FIFO Memory Aperture0 0x46C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO156 FIFO Memory Aperture0 0x470 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO157 FIFO Memory Aperture0 0x474 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO158 FIFO Memory Aperture0 0x478 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO159 FIFO Memory Aperture0 0x47C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO16 FIFO Memory Aperture0 0x240 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO160 FIFO Memory Aperture0 0x480 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO161 FIFO Memory Aperture0 0x484 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO162 FIFO Memory Aperture0 0x488 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO163 FIFO Memory Aperture0 0x48C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO164 FIFO Memory Aperture0 0x490 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO165 FIFO Memory Aperture0 0x494 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO166 FIFO Memory Aperture0 0x498 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO167 FIFO Memory Aperture0 0x49C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO168 FIFO Memory Aperture0 0x4A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO169 FIFO Memory Aperture0 0x4A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO17 FIFO Memory Aperture0 0x244 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO170 FIFO Memory Aperture0 0x4A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO171 FIFO Memory Aperture0 0x4AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO172 FIFO Memory Aperture0 0x4B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO173 FIFO Memory Aperture0 0x4B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO174 FIFO Memory Aperture0 0x4B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO175 FIFO Memory Aperture0 0x4BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO176 FIFO Memory Aperture0 0x4C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO177 FIFO Memory Aperture0 0x4C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO178 FIFO Memory Aperture0 0x4C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO179 FIFO Memory Aperture0 0x4CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO18 FIFO Memory Aperture0 0x248 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO180 FIFO Memory Aperture0 0x4D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO181 FIFO Memory Aperture0 0x4D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO182 FIFO Memory Aperture0 0x4D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO183 FIFO Memory Aperture0 0x4DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO184 FIFO Memory Aperture0 0x4E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO185 FIFO Memory Aperture0 0x4E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO186 FIFO Memory Aperture0 0x4E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO187 FIFO Memory Aperture0 0x4EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO188 FIFO Memory Aperture0 0x4F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO189 FIFO Memory Aperture0 0x4F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO19 FIFO Memory Aperture0 0x24C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO190 FIFO Memory Aperture0 0x4F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO191 FIFO Memory Aperture0 0x4FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO192 FIFO Memory Aperture0 0x500 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO193 FIFO Memory Aperture0 0x504 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO194 FIFO Memory Aperture0 0x508 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO195 FIFO Memory Aperture0 0x50C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO196 FIFO Memory Aperture0 0x510 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO197 FIFO Memory Aperture0 0x514 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO198 FIFO Memory Aperture0 0x518 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO199 FIFO Memory Aperture0 0x51C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO2 FIFO Memory Aperture0 0x208 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO20 FIFO Memory Aperture0 0x250 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO200 FIFO Memory Aperture0 0x520 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO201 FIFO Memory Aperture0 0x524 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO202 FIFO Memory Aperture0 0x528 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO203 FIFO Memory Aperture0 0x52C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO204 FIFO Memory Aperture0 0x530 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO205 FIFO Memory Aperture0 0x534 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO206 FIFO Memory Aperture0 0x538 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO207 FIFO Memory Aperture0 0x53C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO208 FIFO Memory Aperture0 0x540 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO209 FIFO Memory Aperture0 0x544 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO21 FIFO Memory Aperture0 0x254 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO210 FIFO Memory Aperture0 0x548 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO211 FIFO Memory Aperture0 0x54C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO212 FIFO Memory Aperture0 0x550 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO213 FIFO Memory Aperture0 0x554 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO214 FIFO Memory Aperture0 0x558 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO215 FIFO Memory Aperture0 0x55C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO216 FIFO Memory Aperture0 0x560 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO217 FIFO Memory Aperture0 0x564 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO218 FIFO Memory Aperture0 0x568 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO219 FIFO Memory Aperture0 0x56C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO22 FIFO Memory Aperture0 0x258 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO220 FIFO Memory Aperture0 0x570 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO221 FIFO Memory Aperture0 0x574 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO222 FIFO Memory Aperture0 0x578 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO223 FIFO Memory Aperture0 0x57C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO224 FIFO Memory Aperture0 0x580 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO225 FIFO Memory Aperture0 0x584 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO226 FIFO Memory Aperture0 0x588 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO227 FIFO Memory Aperture0 0x58C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO228 FIFO Memory Aperture0 0x590 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO229 FIFO Memory Aperture0 0x594 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO23 FIFO Memory Aperture0 0x25C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO230 FIFO Memory Aperture0 0x598 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO231 FIFO Memory Aperture0 0x59C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO232 FIFO Memory Aperture0 0x5A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO233 FIFO Memory Aperture0 0x5A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO234 FIFO Memory Aperture0 0x5A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO235 FIFO Memory Aperture0 0x5AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO236 FIFO Memory Aperture0 0x5B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO237 FIFO Memory Aperture0 0x5B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO238 FIFO Memory Aperture0 0x5B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO239 FIFO Memory Aperture0 0x5BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO24 FIFO Memory Aperture0 0x260 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO240 FIFO Memory Aperture0 0x5C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO241 FIFO Memory Aperture0 0x5C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO242 FIFO Memory Aperture0 0x5C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO243 FIFO Memory Aperture0 0x5CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO244 FIFO Memory Aperture0 0x5D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO245 FIFO Memory Aperture0 0x5D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO246 FIFO Memory Aperture0 0x5D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO247 FIFO Memory Aperture0 0x5DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO248 FIFO Memory Aperture0 0x5E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO249 FIFO Memory Aperture0 0x5E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO25 FIFO Memory Aperture0 0x264 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO250 FIFO Memory Aperture0 0x5E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO251 FIFO Memory Aperture0 0x5EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO252 FIFO Memory Aperture0 0x5F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO253 FIFO Memory Aperture0 0x5F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO254 FIFO Memory Aperture0 0x5F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO255 FIFO Memory Aperture0 0x5FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO26 FIFO Memory Aperture0 0x268 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO27 FIFO Memory Aperture0 0x26C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO28 FIFO Memory Aperture0 0x270 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO29 FIFO Memory Aperture0 0x274 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO3 FIFO Memory Aperture0 0x20C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO30 FIFO Memory Aperture0 0x278 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO31 FIFO Memory Aperture0 0x27C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO32 FIFO Memory Aperture0 0x280 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO33 FIFO Memory Aperture0 0x284 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO34 FIFO Memory Aperture0 0x288 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO35 FIFO Memory Aperture0 0x28C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO36 FIFO Memory Aperture0 0x290 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO37 FIFO Memory Aperture0 0x294 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO38 FIFO Memory Aperture0 0x298 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO39 FIFO Memory Aperture0 0x29C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO4 FIFO Memory Aperture0 0x210 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO40 FIFO Memory Aperture0 0x2A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO41 FIFO Memory Aperture0 0x2A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO42 FIFO Memory Aperture0 0x2A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO43 FIFO Memory Aperture0 0x2AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO44 FIFO Memory Aperture0 0x2B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO45 FIFO Memory Aperture0 0x2B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO46 FIFO Memory Aperture0 0x2B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO47 FIFO Memory Aperture0 0x2BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO48 FIFO Memory Aperture0 0x2C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO49 FIFO Memory Aperture0 0x2C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO5 FIFO Memory Aperture0 0x214 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO50 FIFO Memory Aperture0 0x2C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO51 FIFO Memory Aperture0 0x2CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO52 FIFO Memory Aperture0 0x2D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO53 FIFO Memory Aperture0 0x2D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO54 FIFO Memory Aperture0 0x2D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO55 FIFO Memory Aperture0 0x2DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO56 FIFO Memory Aperture0 0x2E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO57 FIFO Memory Aperture0 0x2E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO58 FIFO Memory Aperture0 0x2E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO59 FIFO Memory Aperture0 0x2EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO6 FIFO Memory Aperture0 0x218 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO60 FIFO Memory Aperture0 0x2F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO61 FIFO Memory Aperture0 0x2F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO62 FIFO Memory Aperture0 0x2F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO63 FIFO Memory Aperture0 0x2FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO64 FIFO Memory Aperture0 0x300 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO65 FIFO Memory Aperture0 0x304 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO66 FIFO Memory Aperture0 0x308 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO67 FIFO Memory Aperture0 0x30C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO68 FIFO Memory Aperture0 0x310 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO69 FIFO Memory Aperture0 0x314 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO7 FIFO Memory Aperture0 0x21C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO70 FIFO Memory Aperture0 0x318 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO71 FIFO Memory Aperture0 0x31C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO72 FIFO Memory Aperture0 0x320 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO73 FIFO Memory Aperture0 0x324 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO74 FIFO Memory Aperture0 0x328 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO75 FIFO Memory Aperture0 0x32C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO76 FIFO Memory Aperture0 0x330 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO77 FIFO Memory Aperture0 0x334 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO78 FIFO Memory Aperture0 0x338 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO79 FIFO Memory Aperture0 0x33C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO8 FIFO Memory Aperture0 0x220 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO80 FIFO Memory Aperture0 0x340 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO81 FIFO Memory Aperture0 0x344 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO82 FIFO Memory Aperture0 0x348 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO83 FIFO Memory Aperture0 0x34C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO84 FIFO Memory Aperture0 0x350 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO85 FIFO Memory Aperture0 0x354 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO86 FIFO Memory Aperture0 0x358 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO87 FIFO Memory Aperture0 0x35C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO88 FIFO Memory Aperture0 0x360 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO89 FIFO Memory Aperture0 0x364 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO9 FIFO Memory Aperture0 0x224 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO90 FIFO Memory Aperture0 0x368 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO91 FIFO Memory Aperture0 0x36C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO92 FIFO Memory Aperture0 0x370 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO93 FIFO Memory Aperture0 0x374 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO94 FIFO Memory Aperture0 0x378 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO95 FIFO Memory Aperture0 0x37C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO96 FIFO Memory Aperture0 0x380 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO97 FIFO Memory Aperture0 0x384 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO98 FIFO Memory Aperture0 0x388 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO99 FIFO Memory Aperture0 0x38C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO[0] FIFO Memory Aperture0 0x400 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[100] FIFO Memory Aperture0 0x11AE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[101] FIFO Memory Aperture0 0x11E7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[102] FIFO Memory Aperture0 0x12214 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[103] FIFO Memory Aperture0 0x125B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[104] FIFO Memory Aperture0 0x12950 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[105] FIFO Memory Aperture0 0x12CF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[106] FIFO Memory Aperture0 0x1309C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[107] FIFO Memory Aperture0 0x13448 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[108] FIFO Memory Aperture0 0x137F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[109] FIFO Memory Aperture0 0x13BAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[10] FIFO Memory Aperture0 0x18DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[110] FIFO Memory Aperture0 0x13F64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[111] FIFO Memory Aperture0 0x14320 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[112] FIFO Memory Aperture0 0x146E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[113] FIFO Memory Aperture0 0x14AA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[114] FIFO Memory Aperture0 0x14E6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[115] FIFO Memory Aperture0 0x15238 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[116] FIFO Memory Aperture0 0x15608 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[117] FIFO Memory Aperture0 0x159DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[118] FIFO Memory Aperture0 0x15DB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[119] FIFO Memory Aperture0 0x16190 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[11] FIFO Memory Aperture0 0x1B08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[120] FIFO Memory Aperture0 0x16570 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[121] FIFO Memory Aperture0 0x16954 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[122] FIFO Memory Aperture0 0x16D3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[123] FIFO Memory Aperture0 0x17128 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[124] FIFO Memory Aperture0 0x17518 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[125] FIFO Memory Aperture0 0x1790C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[126] FIFO Memory Aperture0 0x17D04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[127] FIFO Memory Aperture0 0x18100 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[128] FIFO Memory Aperture0 0x18500 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[129] FIFO Memory Aperture0 0x18904 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[12] FIFO Memory Aperture0 0x1D38 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[130] FIFO Memory Aperture0 0x18D0C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[131] FIFO Memory Aperture0 0x19118 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[132] FIFO Memory Aperture0 0x19528 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[133] FIFO Memory Aperture0 0x1993C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[134] FIFO Memory Aperture0 0x19D54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[135] FIFO Memory Aperture0 0x1A170 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[136] FIFO Memory Aperture0 0x1A590 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[137] FIFO Memory Aperture0 0x1A9B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[138] FIFO Memory Aperture0 0x1ADDC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[139] FIFO Memory Aperture0 0x1B208 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[13] FIFO Memory Aperture0 0x1F6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[140] FIFO Memory Aperture0 0x1B638 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[141] FIFO Memory Aperture0 0x1BA6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[142] FIFO Memory Aperture0 0x1BEA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[143] FIFO Memory Aperture0 0x1C2E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[144] FIFO Memory Aperture0 0x1C720 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[145] FIFO Memory Aperture0 0x1CB64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[146] FIFO Memory Aperture0 0x1CFAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[147] FIFO Memory Aperture0 0x1D3F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[148] FIFO Memory Aperture0 0x1D848 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[149] FIFO Memory Aperture0 0x1DC9C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[14] FIFO Memory Aperture0 0x21A4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[150] FIFO Memory Aperture0 0x1E0F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[151] FIFO Memory Aperture0 0x1E550 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[152] FIFO Memory Aperture0 0x1E9B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[153] FIFO Memory Aperture0 0x1EE14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[154] FIFO Memory Aperture0 0x1F27C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[155] FIFO Memory Aperture0 0x1F6E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[156] FIFO Memory Aperture0 0x1FB58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[157] FIFO Memory Aperture0 0x1FFCC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[158] FIFO Memory Aperture0 0x20444 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[159] FIFO Memory Aperture0 0x208C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[15] FIFO Memory Aperture0 0x23E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[160] FIFO Memory Aperture0 0x20D40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[161] FIFO Memory Aperture0 0x211C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[162] FIFO Memory Aperture0 0x2164C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[163] FIFO Memory Aperture0 0x21AD8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[164] FIFO Memory Aperture0 0x21F68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[165] FIFO Memory Aperture0 0x223FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[166] FIFO Memory Aperture0 0x22894 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[167] FIFO Memory Aperture0 0x22D30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[168] FIFO Memory Aperture0 0x231D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[169] FIFO Memory Aperture0 0x23674 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[16] FIFO Memory Aperture0 0x2620 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[170] FIFO Memory Aperture0 0x23B1C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[171] FIFO Memory Aperture0 0x23FC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[172] FIFO Memory Aperture0 0x24478 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[173] FIFO Memory Aperture0 0x2492C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[174] FIFO Memory Aperture0 0x24DE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[175] FIFO Memory Aperture0 0x252A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[176] FIFO Memory Aperture0 0x25760 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[177] FIFO Memory Aperture0 0x25C24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[178] FIFO Memory Aperture0 0x260EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[179] FIFO Memory Aperture0 0x265B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[17] FIFO Memory Aperture0 0x2864 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[180] FIFO Memory Aperture0 0x26A88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[181] FIFO Memory Aperture0 0x26F5C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[182] FIFO Memory Aperture0 0x27434 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[183] FIFO Memory Aperture0 0x27910 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[184] FIFO Memory Aperture0 0x27DF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[185] FIFO Memory Aperture0 0x282D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[186] FIFO Memory Aperture0 0x287BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[187] FIFO Memory Aperture0 0x28CA8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[188] FIFO Memory Aperture0 0x29198 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[189] FIFO Memory Aperture0 0x2968C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[18] FIFO Memory Aperture0 0x2AAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[190] FIFO Memory Aperture0 0x29B84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[191] FIFO Memory Aperture0 0x2A080 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[192] FIFO Memory Aperture0 0x2A580 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[193] FIFO Memory Aperture0 0x2AA84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[194] FIFO Memory Aperture0 0x2AF8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[195] FIFO Memory Aperture0 0x2B498 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[196] FIFO Memory Aperture0 0x2B9A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[197] FIFO Memory Aperture0 0x2BEBC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[198] FIFO Memory Aperture0 0x2C3D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[199] FIFO Memory Aperture0 0x2C8F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[19] FIFO Memory Aperture0 0x2CF8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[1] FIFO Memory Aperture0 0x604 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[200] FIFO Memory Aperture0 0x2CE10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[201] FIFO Memory Aperture0 0x2D334 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[202] FIFO Memory Aperture0 0x2D85C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[203] FIFO Memory Aperture0 0x2DD88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[204] FIFO Memory Aperture0 0x2E2B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[205] FIFO Memory Aperture0 0x2E7EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[206] FIFO Memory Aperture0 0x2ED24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[207] FIFO Memory Aperture0 0x2F260 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[208] FIFO Memory Aperture0 0x2F7A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[209] FIFO Memory Aperture0 0x2FCE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[20] FIFO Memory Aperture0 0x2F48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[210] FIFO Memory Aperture0 0x3022C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[211] FIFO Memory Aperture0 0x30778 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[212] FIFO Memory Aperture0 0x30CC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[213] FIFO Memory Aperture0 0x3121C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[214] FIFO Memory Aperture0 0x31774 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[215] FIFO Memory Aperture0 0x31CD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[216] FIFO Memory Aperture0 0x32230 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[217] FIFO Memory Aperture0 0x32794 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[218] FIFO Memory Aperture0 0x32CFC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[219] FIFO Memory Aperture0 0x33268 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[21] FIFO Memory Aperture0 0x319C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[220] FIFO Memory Aperture0 0x337D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[221] FIFO Memory Aperture0 0x33D4C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[222] FIFO Memory Aperture0 0x342C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[223] FIFO Memory Aperture0 0x34840 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[224] FIFO Memory Aperture0 0x34DC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[225] FIFO Memory Aperture0 0x35344 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[226] FIFO Memory Aperture0 0x358CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[227] FIFO Memory Aperture0 0x35E58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[228] FIFO Memory Aperture0 0x363E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[229] FIFO Memory Aperture0 0x3697C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[22] FIFO Memory Aperture0 0x33F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[230] FIFO Memory Aperture0 0x36F14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[231] FIFO Memory Aperture0 0x374B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[232] FIFO Memory Aperture0 0x37A50 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[233] FIFO Memory Aperture0 0x37FF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[234] FIFO Memory Aperture0 0x3859C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[235] FIFO Memory Aperture0 0x38B48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[236] FIFO Memory Aperture0 0x390F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[237] FIFO Memory Aperture0 0x396AC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[238] FIFO Memory Aperture0 0x39C64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[239] FIFO Memory Aperture0 0x3A220 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[23] FIFO Memory Aperture0 0x3650 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[240] FIFO Memory Aperture0 0x3A7E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[241] FIFO Memory Aperture0 0x3ADA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[242] FIFO Memory Aperture0 0x3B36C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[243] FIFO Memory Aperture0 0x3B938 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[244] FIFO Memory Aperture0 0x3BF08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[245] FIFO Memory Aperture0 0x3C4DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[246] FIFO Memory Aperture0 0x3CAB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[247] FIFO Memory Aperture0 0x3D090 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[248] FIFO Memory Aperture0 0x3D670 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[249] FIFO Memory Aperture0 0x3DC54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[24] FIFO Memory Aperture0 0x38B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[250] FIFO Memory Aperture0 0x3E23C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[251] FIFO Memory Aperture0 0x3E828 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[252] FIFO Memory Aperture0 0x3EE18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[253] FIFO Memory Aperture0 0x3F40C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[254] FIFO Memory Aperture0 0x3FA04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[255] FIFO Memory Aperture0 0x40000 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[25] FIFO Memory Aperture0 0x3B14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[26] FIFO Memory Aperture0 0x3D7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[27] FIFO Memory Aperture0 0x3FE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[28] FIFO Memory Aperture0 0x4258 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[29] FIFO Memory Aperture0 0x44CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[2] FIFO Memory Aperture0 0x80C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[30] FIFO Memory Aperture0 0x4744 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[31] FIFO Memory Aperture0 0x49C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[32] FIFO Memory Aperture0 0x4C40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[33] FIFO Memory Aperture0 0x4EC4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[34] FIFO Memory Aperture0 0x514C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[35] FIFO Memory Aperture0 0x53D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[36] FIFO Memory Aperture0 0x5668 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[37] FIFO Memory Aperture0 0x58FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[38] FIFO Memory Aperture0 0x5B94 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[39] FIFO Memory Aperture0 0x5E30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[3] FIFO Memory Aperture0 0xA18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[40] FIFO Memory Aperture0 0x60D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[41] FIFO Memory Aperture0 0x6374 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[42] FIFO Memory Aperture0 0x661C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[43] FIFO Memory Aperture0 0x68C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[44] FIFO Memory Aperture0 0x6B78 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[45] FIFO Memory Aperture0 0x6E2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[46] FIFO Memory Aperture0 0x70E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[47] FIFO Memory Aperture0 0x73A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[48] FIFO Memory Aperture0 0x7660 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[49] FIFO Memory Aperture0 0x7924 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[4] FIFO Memory Aperture0 0xC28 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[50] FIFO Memory Aperture0 0x7BEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[51] FIFO Memory Aperture0 0x7EB8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[52] FIFO Memory Aperture0 0x8188 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[53] FIFO Memory Aperture0 0x845C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[54] FIFO Memory Aperture0 0x8734 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[55] FIFO Memory Aperture0 0x8A10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[56] FIFO Memory Aperture0 0x8CF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[57] FIFO Memory Aperture0 0x8FD4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[58] FIFO Memory Aperture0 0x92BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[59] FIFO Memory Aperture0 0x95A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[5] FIFO Memory Aperture0 0xE3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[60] FIFO Memory Aperture0 0x9898 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[61] FIFO Memory Aperture0 0x9B8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[62] FIFO Memory Aperture0 0x9E84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[63] FIFO Memory Aperture0 0xA180 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[64] FIFO Memory Aperture0 0xA480 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[65] FIFO Memory Aperture0 0xA784 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[66] FIFO Memory Aperture0 0xAA8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[67] FIFO Memory Aperture0 0xAD98 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[68] FIFO Memory Aperture0 0xB0A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[69] FIFO Memory Aperture0 0xB3BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[6] FIFO Memory Aperture0 0x1054 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[70] FIFO Memory Aperture0 0xB6D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[71] FIFO Memory Aperture0 0xB9F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[72] FIFO Memory Aperture0 0xBD10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[73] FIFO Memory Aperture0 0xC034 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[74] FIFO Memory Aperture0 0xC35C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[75] FIFO Memory Aperture0 0xC688 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[76] FIFO Memory Aperture0 0xC9B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[77] FIFO Memory Aperture0 0xCCEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[78] FIFO Memory Aperture0 0xD024 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[79] FIFO Memory Aperture0 0xD360 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[7] FIFO Memory Aperture0 0x1270 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[80] FIFO Memory Aperture0 0xD6A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[81] FIFO Memory Aperture0 0xD9E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[82] FIFO Memory Aperture0 0xDD2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[83] FIFO Memory Aperture0 0xE078 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[84] FIFO Memory Aperture0 0xE3C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[85] FIFO Memory Aperture0 0xE71C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[86] FIFO Memory Aperture0 0xEA74 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[87] FIFO Memory Aperture0 0xEDD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[88] FIFO Memory Aperture0 0xF130 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[89] FIFO Memory Aperture0 0xF494 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[8] FIFO Memory Aperture0 0x1490 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[90] FIFO Memory Aperture0 0xF7FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[91] FIFO Memory Aperture0 0xFB68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[92] FIFO Memory Aperture0 0xFED8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[93] FIFO Memory Aperture0 0x1024C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[94] FIFO Memory Aperture0 0x105C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[95] FIFO Memory Aperture0 0x10940 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[96] FIFO Memory Aperture0 0x10CC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[97] FIFO Memory Aperture0 0x11044 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[98] FIFO Memory Aperture0 0x113CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[99] FIFO Memory Aperture0 0x11758 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[9] FIFO Memory Aperture0 0x16B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DMADONE DMA Transfer completed Interrupt Disable 25 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only SDIOIRQforSlotA 8 1 write-only SDIOIRQforSlotB 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DMADONE DMA Transfer completed Interrupt Enable 25 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only SDIOIRQforSlotA 8 1 write-only SDIOIRQforSlotB 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only CMDRDY Command Ready Interrupt Mask 0 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DMADONE DMA Transfer Completed Interrupt Mask 25 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only SDIOIRQforSlotA 8 1 read-only SDIOIRQforSlotB 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CLKDIV Clock Divider 0 8 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF Read Proof Enable 11 1 read-write WRPROOF Write Proof Enable 12 1 read-write RDR Receive Data Register 0x30 32 read-only n 0x0 0x0 DATA Data to Read 0 32 read-only RSPR0 Response Register 0x20 32 read-only n RSP Response 0 32 read-only RSPR1 Response Register 0x24 32 read-only n RSP Response 0 32 read-only RSPR2 Response Register 0x28 32 read-only n RSP Response 0 32 read-only RSPR3 Response Register 0x2C 32 read-only n RSP Response 0 32 read-only RSPR[0] Response Register 0x40 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[1] Response Register 0x64 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[2] Response Register 0x8C 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[3] Response Register 0xB8 32 read-only n 0x0 0x0 RSP Response 0 32 read-only SDCR SD/SDIO Card Register 0xC 32 read-write n 0x0 0x0 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bits 0x2 8 8 bits 0x3 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0x0 SLOTB SDCARD/SDIO Slot B selected 0x1 SLOTC - 0x2 SLOTD - 0x3 SR Status Register 0x40 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received 28 1 read-only ACKRCVE Boot Operation Acknowledge Error 29 1 read-only BLKE Data Block Ended 3 1 read-only BLKOVRE DMA Block Overrun Error 24 1 read-only CMDRDY Command Ready 0 1 read-only CSRCV CE-ATA Completion Signal Received 13 1 read-only CSTOE Completion Signal Time-out Error 23 1 read-only DCRCE Data CRC Error 21 1 read-only DMADONE DMA Transfer done 25 1 read-only DTIP Data Transfer in Progress 4 1 read-only DTOE Data Time-out Error 22 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only OVRE Overrun 30 1 read-only RCRCE Response CRC Error 18 1 read-only RDIRE Response Direction Error 17 1 read-only RENDE Response End Bit Error 19 1 read-only RINDE Response Index Error 16 1 read-only RTOE Response Time-out Error 20 1 read-only RXRDY Receiver Ready 1 1 read-only SDIOIRQforSlotA 8 1 read-only SDIOIRQforSlotB 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only TXRDY Transmit Ready 2 1 read-only UNRE Underrun 31 1 read-only XFRDONE Transfer Done flag 27 1 read-only TDR Transmit Data Register 0x34 32 write-only n 0x0 0x0 DATA Data to Write 0 32 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4349 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only MATRIX AHB Bus Matrix MATRIX 0x0 0x0 0x200 registers n CCFG_SYSIO System I/O Configuration register 0x114 32 read-write n 0x0 0x0 SYSIO12 PC0 or ERASE Assignment 12 1 read-write MCFG0 Master Configuration Register 0x0 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG1 Master Configuration Register 0x4 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG2 Master Configuration Register 0x8 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG3 Master Configuration Register 0xC 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG4 Master Configuration Register 0x10 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG5 Master Configuration Register 0x14 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write MCFG[0] Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MCFG[1] Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MCFG[2] Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MCFG[3] Master Configuration Register 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MCFG[4] Master Configuration Register 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MCFG[5] Master Configuration Register 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write MRCR Master Remap Control Register 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command Bit for AHB Master 0 0 1 read-write RCB1 Remap Command Bit for AHB Master 1 1 1 read-write RCB2 Remap Command Bit for AHB Master 2 2 1 read-write RCB3 Remap Command Bit for AHB Master 3 3 1 read-write RCB4 Remap Command Bit for AHB Master 4 4 2 read-write RCB5 Remap Command Bit for AHB Master 5 6 1 read-write PRAS0 Priority Register A for Slave 0 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS1 Priority Register A for Slave 1 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS2 Priority Register A for Slave 2 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS3 Priority Register A for Slave 3 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS4 Priority Register A for Slave 4 0xA0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS5 Priority Register A for Slave 5 0xA8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS6 Priority Register A for Slave 6 0xB0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS7 Priority Register A for Slave 7 0xB8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write PRAS8 Priority Register A for Slave 8 0xC0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write SCFG0 Slave Configuration Register 0x40 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG1 Slave Configuration Register 0x44 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG2 Slave Configuration Register 0x48 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG3 Slave Configuration Register 0x4C 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG4 Slave Configuration Register 0x50 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG5 Slave Configuration Register 0x54 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG6 Slave Configuration Register 0x58 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG7 Slave Configuration Register 0x5C 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG8 Slave Configuration Register 0x60 32 read-write n ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[0] Slave Configuration Register 0x80 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[1] Slave Configuration Register 0xC4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[2] Slave Configuration Register 0x10C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[3] Slave Configuration Register 0x158 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[4] Slave Configuration Register 0x1A8 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[5] Slave Configuration Register 0x1FC 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[6] Slave Configuration Register 0x254 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[7] Slave Configuration Register 0x2B0 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[8] Slave Configuration Register 0x310 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write WPMR Write Protect Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protect ENable 0 1 read-write WPKEY Write Protect KEY (Write-only) 8 24 read-write WPSR Write Protect Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOA Parallel Input/Output Controller A PIO 0x0 0x0 0x200 registers n PIOA 11 ABSR Peripheral AB Select Register 0x70 32 read-write n 0x0 0x0 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P2 Peripheral A Select. 2 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P3 Peripheral A Select. 3 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write AIMDR Additional Interrupt Modes Disables Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P2 Peripheral CD Status. 2 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P3 Peripheral CD Status. 3 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DIFSR Debouncing Input Filter Select Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only FELLSR Falling Edge/Low Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P2 Lock Status. 2 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P3 Lock Status. 3 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P2 Level Interrupt Selection. 2 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P3 Level Interrupt Selection. 3 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P2 Multi Drive Disable. 2 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P3 Multi Drive Disable. 3 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P2 Multi Drive Enable. 2 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P3 Multi Drive Enable. 3 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P2 Multi Drive Status. 2 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P3 Multi Drive Status. 3 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P2 Output Write Disable. 2 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P3 Output Write Disable. 3 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P2 Output Write Enable. 2 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P3 Output Write Enable. 3 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P2 Output Write Status. 2 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P3 Output Write Status. 3 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P2 Pull Up Disable. 2 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P3 Pull Up Disable. 3 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P2 Pull Up Enable. 2 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P3 Pull Up Enable. 3 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P2 Pull Up Status. 2 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P3 Pull Up Status. 3 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only REHLSR Rising Edge/ High Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x80 32 write-only n 0x0 0x0 P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOB Parallel Input/Output Controller B PIO 0x0 0x0 0x200 registers n PIOB 12 ABSR Peripheral AB Select Register 0x70 32 read-write n 0x0 0x0 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P2 Peripheral A Select. 2 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P3 Peripheral A Select. 3 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write AIMDR Additional Interrupt Modes Disables Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P2 Peripheral CD Status. 2 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P3 Peripheral CD Status. 3 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DIFSR Debouncing Input Filter Select Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only FELLSR Falling Edge/Low Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P2 Lock Status. 2 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P3 Lock Status. 3 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P2 Level Interrupt Selection. 2 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P3 Level Interrupt Selection. 3 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P2 Multi Drive Disable. 2 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P3 Multi Drive Disable. 3 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P2 Multi Drive Enable. 2 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P3 Multi Drive Enable. 3 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P2 Multi Drive Status. 2 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P3 Multi Drive Status. 3 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P2 Output Write Disable. 2 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P3 Output Write Disable. 3 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P2 Output Write Enable. 2 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P3 Output Write Enable. 3 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P2 Output Write Status. 2 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P3 Output Write Status. 3 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P2 Pull Up Disable. 2 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P3 Pull Up Disable. 3 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P2 Pull Up Enable. 2 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P3 Pull Up Enable. 3 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P2 Pull Up Status. 2 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P3 Pull Up Status. 3 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only REHLSR Rising Edge/ High Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x80 32 write-only n 0x0 0x0 P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOC Parallel Input/Output Controller C PIO 0x0 0x0 0x200 registers n PIOC 13 ABSR Peripheral AB Select Register 0x70 32 read-write n 0x0 0x0 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P2 Peripheral A Select. 2 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P3 Peripheral A Select. 3 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write AIMDR Additional Interrupt Modes Disables Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P2 Peripheral CD Status. 2 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P3 Peripheral CD Status. 3 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DIFSR Debouncing Input Filter Select Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only FELLSR Falling Edge/Low Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P2 Lock Status. 2 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P3 Lock Status. 3 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P2 Level Interrupt Selection. 2 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P3 Level Interrupt Selection. 3 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P2 Multi Drive Disable. 2 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P3 Multi Drive Disable. 3 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P2 Multi Drive Enable. 2 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P3 Multi Drive Enable. 3 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P2 Multi Drive Status. 2 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P3 Multi Drive Status. 3 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P2 Output Write Disable. 2 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P3 Output Write Disable. 3 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P2 Output Write Enable. 2 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P3 Output Write Enable. 3 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P2 Output Write Status. 2 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P3 Output Write Status. 3 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P2 Pull Up Disable. 2 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P3 Pull Up Disable. 3 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P2 Pull Up Enable. 2 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P3 Pull Up Enable. 3 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P2 Pull Up Status. 2 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P3 Pull Up Status. 3 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only REHLSR Rising Edge/ High Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x80 32 write-only n 0x0 0x0 P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOD Parallel Input/Output Controller D PIO 0x0 0x0 0x200 registers n PIOD 14 ABSR Peripheral AB Select Register 0x70 32 read-write n 0x0 0x0 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P2 Peripheral A Select. 2 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P3 Peripheral A Select. 3 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write AIMDR Additional Interrupt Modes Disables Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P2 Peripheral CD Status. 2 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P3 Peripheral CD Status. 3 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DIFSR Debouncing Input Filter Select Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only FELLSR Falling Edge/Low Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P2 Lock Status. 2 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P3 Lock Status. 3 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P2 Level Interrupt Selection. 2 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P3 Level Interrupt Selection. 3 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P2 Multi Drive Disable. 2 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P3 Multi Drive Disable. 3 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P2 Multi Drive Enable. 2 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P3 Multi Drive Enable. 3 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P2 Multi Drive Status. 2 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P3 Multi Drive Status. 3 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P2 Output Write Disable. 2 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P3 Output Write Disable. 3 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P2 Output Write Enable. 2 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P3 Output Write Enable. 3 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P2 Output Write Status. 2 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P3 Output Write Status. 3 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P2 Pull Up Disable. 2 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P3 Pull Up Disable. 3 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P2 Pull Up Enable. 2 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P3 Pull Up Enable. 3 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P2 Pull Up Status. 2 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P3 Pull Up Status. 3 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only REHLSR Rising Edge/ High Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x80 32 write-only n 0x0 0x0 P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PMC Power Management Controller PMC 0x0 0x0 0x140 registers n PMC 5 CKGR_MCFR Main Clock Frequency Register 0x24 32 read-only n 0x0 0x0 MAINF Main Clock Frequency 0 16 read-only MAINFRDY Main Clock Ready 16 1 read-only CKGR_MOR Main Oscillator Register 0x20 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 25 1 read-write KEY Write Access Password 16 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x37 MOSCRCEN Main On-Chip RC Oscillator Enable 3 1 read-write MOSCRCF Main On-Chip RC Oscillator Frequency Selection 4 3 read-write 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 0x0 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x1 12_MHz The Fast RC Oscillator Frequency is at 12 MHz 0x2 MOSCSEL Main Oscillator Selection 24 1 read-write MOSCXTBY Main Crystal Oscillator Bypass 1 1 read-write MOSCXTEN Main Crystal Oscillator Enable 0 1 read-write MOSCXTST Main Crystal Oscillator Start-up Time 8 8 read-write CKGR_PLLAR PLLA Register 0x28 32 read-write n 0x0 0x0 DIVA Divider 0 8 read-write MULA PLLA Multiplier 16 11 read-write ONE Must Be Set to 1 29 1 read-write PLLACOUNT PLLA Counter 8 6 read-write CKGR_UCKR UTMI Clock Register 0x1C 32 read-write n 0x0 0x0 UPLLCOUNT UTMI PLL Start-up Time 20 4 read-write UPLLEN UTMI PLL Enable 16 1 read-write FOCR Fault Output Clear Register 0x78 32 write-only n 0x0 0x0 FOCLR Fault Output Clear 0 1 write-only FSMR Fast Start-up Mode Register 0x70 32 read-write n 0x0 0x0 FSTT0 Fast Start-up Input Enable 0 0 1 read-write FSTT1 Fast Start-up Input Enable 1 1 1 read-write FSTT10 Fast Start-up Input Enable 10 10 1 read-write FSTT11 Fast Start-up Input Enable 11 11 1 read-write FSTT12 Fast Start-up Input Enable 12 12 1 read-write FSTT13 Fast Start-up Input Enable 13 13 1 read-write FSTT14 Fast Start-up Input Enable 14 14 1 read-write FSTT15 Fast Start-up Input Enable 15 15 1 read-write FSTT2 Fast Start-up Input Enable 2 2 1 read-write FSTT3 Fast Start-up Input Enable 3 3 1 read-write FSTT4 Fast Start-up Input Enable 4 4 1 read-write FSTT5 Fast Start-up Input Enable 5 5 1 read-write FSTT6 Fast Start-up Input Enable 6 6 1 read-write FSTT7 Fast Start-up Input Enable 7 7 1 read-write FSTT8 Fast Start-up Input Enable 8 8 1 read-write FSTT9 Fast Start-up Input Enable 9 9 1 read-write LPM Low Power Mode 20 1 read-write RTCAL RTC Alarm Enable 17 1 read-write RTTAL RTT Alarm Enable 16 1 read-write USBAL USB Alarm Enable 18 1 read-write FSPR Fast Start-up Polarity Register 0x74 32 read-write n 0x0 0x0 FSTP0 Fast Start-up Input Polarityx 0 1 read-write FSTP1 Fast Start-up Input Polarityx 1 1 read-write FSTP10 Fast Start-up Input Polarityx 10 1 read-write FSTP11 Fast Start-up Input Polarityx 11 1 read-write FSTP12 Fast Start-up Input Polarityx 12 1 read-write FSTP13 Fast Start-up Input Polarityx 13 1 read-write FSTP14 Fast Start-up Input Polarityx 14 1 read-write FSTP15 Fast Start-up Input Polarityx 15 1 read-write FSTP2 Fast Start-up Input Polarityx 2 1 read-write FSTP3 Fast Start-up Input Polarityx 3 1 read-write FSTP4 Fast Start-up Input Polarityx 4 1 read-write FSTP5 Fast Start-up Input Polarityx 5 1 read-write FSTP6 Fast Start-up Input Polarityx 6 1 read-write FSTP7 Fast Start-up Input Polarityx 7 1 read-write FSTP8 Fast Start-up Input Polarityx 8 1 read-write FSTP9 Fast Start-up Input Polarityx 9 1 read-write IDR Interrupt Disable Register 0x64 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Disable 18 1 write-only LOCKA PLLA Lock Interrupt Disable 1 1 write-only LOCKU UTMI PLL Lock Interrupt Disable 6 1 write-only MCKRDY Master Clock Ready Interrupt Disable 3 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Disable 17 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Disable 16 1 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Disable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x60 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Enable 18 1 write-only LOCKA PLLA Lock Interrupt Enable 1 1 write-only LOCKU UTMI PLL Lock Interrupt Enable 6 1 write-only MCKRDY Master Clock Ready Interrupt Enable 3 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Enable 17 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Enable 16 1 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Enable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x6C 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Mask 18 1 read-only LOCKA PLLA Lock Interrupt Mask 1 1 read-only LOCKU UTMI PLL Lock Interrupt Mask 6 1 read-only MCKRDY Master Clock Ready Interrupt Mask 3 1 read-only MOSCRCS Main On-Chip RC Status Interrupt Mask 17 1 read-only MOSCSELS Main Oscillator Selection Status Interrupt Mask 16 1 read-only MOSCXTS Main Crystal Oscillator Status Interrupt Mask 0 1 read-only PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 read-only PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 read-only PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 read-only MCKR Master Clock Register 0x30 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 2 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 PLLADIV2 PLLA Divisor by 2 12 1 read-write PRES Processor Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 CLK_3 Selected clock divided by 3 0x7 UPLLDIV2 13 1 read-write PCDR0 Peripheral Clock Disable Register 0 0x14 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Disable 10 1 write-only PID11 Peripheral Clock 11 Disable 11 1 write-only PID12 Peripheral Clock 12 Disable 12 1 write-only PID13 Peripheral Clock 13 Disable 13 1 write-only PID14 Peripheral Clock 14 Disable 14 1 write-only PID15 Peripheral Clock 15 Disable 15 1 write-only PID16 Peripheral Clock 16 Disable 16 1 write-only PID17 Peripheral Clock 17 Disable 17 1 write-only PID18 Peripheral Clock 18 Disable 18 1 write-only PID19 Peripheral Clock 19 Disable 19 1 write-only PID20 Peripheral Clock 20 Disable 20 1 write-only PID21 Peripheral Clock 21 Disable 21 1 write-only PID22 Peripheral Clock 22 Disable 22 1 write-only PID23 Peripheral Clock 23 Disable 23 1 write-only PID24 Peripheral Clock 24 Disable 24 1 write-only PID25 Peripheral Clock 25 Disable 25 1 write-only PID26 Peripheral Clock 26 Disable 26 1 write-only PID27 Peripheral Clock 27 Disable 27 1 write-only PID28 Peripheral Clock 28 Disable 28 1 write-only PID29 Peripheral Clock 29 Disable 29 1 write-only PID30 Peripheral Clock 30 Disable 30 1 write-only PID31 Peripheral Clock 31 Disable 31 1 write-only PID8 Peripheral Clock 8 Disable 8 1 write-only PID9 Peripheral Clock 9 Disable 9 1 write-only PCDR1 Peripheral Clock Disable Register 1 0x104 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Disable 0 1 write-only PID33 Peripheral Clock 33 Disable 1 1 write-only PID34 Peripheral Clock 34 Disable 2 1 write-only PID35 Peripheral Clock 35 Disable 3 1 write-only PID36 Peripheral Clock 36 Disable 4 1 write-only PID37 Peripheral Clock 37 Disable 5 1 write-only PID38 Peripheral Clock 38 Disable 6 1 write-only PID39 Peripheral Clock 39 Disable 7 1 write-only PID40 Peripheral Clock 40 Disable 8 1 write-only PID41 Peripheral Clock 41 Disable 9 1 write-only PID42 Peripheral Clock 42 Disable 10 1 write-only PID43 Peripheral Clock 43 Disable 11 1 write-only PID44 Peripheral Clock 44 Disable 12 1 write-only PCER0 Peripheral Clock Enable Register 0 0x10 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Enable 10 1 write-only PID11 Peripheral Clock 11 Enable 11 1 write-only PID12 Peripheral Clock 12 Enable 12 1 write-only PID13 Peripheral Clock 13 Enable 13 1 write-only PID14 Peripheral Clock 14 Enable 14 1 write-only PID15 Peripheral Clock 15 Enable 15 1 write-only PID16 Peripheral Clock 16 Enable 16 1 write-only PID17 Peripheral Clock 17 Enable 17 1 write-only PID18 Peripheral Clock 18 Enable 18 1 write-only PID19 Peripheral Clock 19 Enable 19 1 write-only PID20 Peripheral Clock 20 Enable 20 1 write-only PID21 Peripheral Clock 21 Enable 21 1 write-only PID22 Peripheral Clock 22 Enable 22 1 write-only PID23 Peripheral Clock 23 Enable 23 1 write-only PID24 Peripheral Clock 24 Enable 24 1 write-only PID25 Peripheral Clock 25 Enable 25 1 write-only PID26 Peripheral Clock 26 Enable 26 1 write-only PID27 Peripheral Clock 27 Enable 27 1 write-only PID28 Peripheral Clock 28 Enable 28 1 write-only PID29 Peripheral Clock 29 Enable 29 1 write-only PID30 Peripheral Clock 30 Enable 30 1 write-only PID31 Peripheral Clock 31 Enable 31 1 write-only PID8 Peripheral Clock 8 Enable 8 1 write-only PID9 Peripheral Clock 9 Enable 9 1 write-only PCER1 Peripheral Clock Enable Register 1 0x100 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Enable 0 1 write-only PID33 Peripheral Clock 33 Enable 1 1 write-only PID34 Peripheral Clock 34 Enable 2 1 write-only PID35 Peripheral Clock 35 Enable 3 1 write-only PID36 Peripheral Clock 36 Enable 4 1 write-only PID37 Peripheral Clock 37 Enable 5 1 write-only PID38 Peripheral Clock 38 Enable 6 1 write-only PID39 Peripheral Clock 39 Enable 7 1 write-only PID40 Peripheral Clock 40 Enable 8 1 write-only PID41 Peripheral Clock 41 Enable 9 1 write-only PID42 Peripheral Clock 42 Enable 10 1 write-only PID43 Peripheral Clock 43 Enable 11 1 write-only PID44 Peripheral Clock 44 Enable 12 1 write-only PCK0 Programmable Clock 0 Register 0x40 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK1 Programmable Clock 0 Register 0x44 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK2 Programmable Clock 0 Register 0x48 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[0] Programmable Clock 0 Register 0x80 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[1] Programmable Clock 0 Register 0xC4 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[2] Programmable Clock 0 Register 0x10C 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCR Peripheral Control Register 0x10C 32 read-write n 0x0 0x0 CMD Command 12 1 read-write DIV Divisor Value 16 2 read-write PERIPH_DIV_MCK Peripheral clock is MCK 0x0 PERIPH_DIV2_MCK Peripheral clock is MCK/2 0x1 PERIPH_DIV4_MCK Peripheral clock is MCK/4 0x2 EN Enable 28 1 read-write PID Peripheral ID 0 6 read-write PCSR0 Peripheral Clock Status Register 0 0x18 32 read-only n 0x0 0x0 PID10 Peripheral Clock 10 Status 10 1 read-only PID11 Peripheral Clock 11 Status 11 1 read-only PID12 Peripheral Clock 12 Status 12 1 read-only PID13 Peripheral Clock 13 Status 13 1 read-only PID14 Peripheral Clock 14 Status 14 1 read-only PID15 Peripheral Clock 15 Status 15 1 read-only PID16 Peripheral Clock 16 Status 16 1 read-only PID17 Peripheral Clock 17 Status 17 1 read-only PID18 Peripheral Clock 18 Status 18 1 read-only PID19 Peripheral Clock 19 Status 19 1 read-only PID20 Peripheral Clock 20 Status 20 1 read-only PID21 Peripheral Clock 21 Status 21 1 read-only PID22 Peripheral Clock 22 Status 22 1 read-only PID23 Peripheral Clock 23 Status 23 1 read-only PID24 Peripheral Clock 24 Status 24 1 read-only PID25 Peripheral Clock 25 Status 25 1 read-only PID26 Peripheral Clock 26 Status 26 1 read-only PID27 Peripheral Clock 27 Status 27 1 read-only PID28 Peripheral Clock 28 Status 28 1 read-only PID29 Peripheral Clock 29 Status 29 1 read-only PID30 Peripheral Clock 30 Status 30 1 read-only PID31 Peripheral Clock 31 Status 31 1 read-only PID8 Peripheral Clock 8 Status 8 1 read-only PID9 Peripheral Clock 9 Status 9 1 read-only PCSR1 Peripheral Clock Status Register 1 0x108 32 read-only n 0x0 0x0 PID32 Peripheral Clock 32 Status 0 1 read-only PID33 Peripheral Clock 33 Status 1 1 read-only PID34 Peripheral Clock 34 Status 2 1 read-only PID35 Peripheral Clock 35 Status 3 1 read-only PID36 Peripheral Clock 36 Status 4 1 read-only PID37 Peripheral Clock 37 Status 5 1 read-only PID38 Peripheral Clock 38 Status 6 1 read-only PID39 Peripheral Clock 39 Status 7 1 read-only PID40 Peripheral Clock 40 Status 8 1 read-only PID41 Peripheral Clock 41 Status 9 1 read-only PID42 Peripheral Clock 42 Status 10 1 read-only PID43 Peripheral Clock 43 Status 11 1 read-only PID44 Peripheral Clock 44 Status 12 1 read-only SCDR System Clock Disable Register 0x4 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Disable 8 1 write-only PCK1 Programmable Clock 1 Output Disable 9 1 write-only PCK2 Programmable Clock 2 Output Disable 10 1 write-only UOTGCLK Disable USB OTG Clock (48 MHz, USB_48M) for UTMI 5 1 write-only SCER System Clock Enable Register 0x0 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Enable 8 1 write-only PCK1 Programmable Clock 1 Output Enable 9 1 write-only PCK2 Programmable Clock 2 Output Enable 10 1 write-only UOTGCLK Enable USB OTG Clock (48 MHz, USB_48M) for UTMI 5 1 write-only SCSR System Clock Status Register 0x8 32 read-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Status 8 1 read-only PCK1 Programmable Clock 1 Output Status 9 1 read-only PCK2 Programmable Clock 2 Output Status 10 1 read-only UOTGCLK USB OTG Clock (48 MHz, USB_48M) Clock Status 5 1 read-only SR Status Register 0x68 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event 18 1 read-only CFDS Clock Failure Detector Status 19 1 read-only FOS Clock Failure Detector Fault Output Status 20 1 read-only LOCKA PLLA Lock Status 1 1 read-only LOCKU UTMI PLL Lock Status 6 1 read-only MCKRDY Master Clock Status 3 1 read-only MOSCRCS Main On-Chip RC Oscillator Status 17 1 read-only MOSCSELS Main Oscillator Selection Status 16 1 read-only MOSCXTS Main XTAL Oscillator Status 0 1 read-only OSCSELS Slow Clock Oscillator Selection 7 1 read-only PCKRDY0 Programmable Clock Ready Status 8 1 read-only PCKRDY1 Programmable Clock Ready Status 9 1 read-only PCKRDY2 Programmable Clock Ready Status 10 1 read-only USB USB Clock Register 0x38 32 read-write n 0x0 0x0 USBDIV Divider for USB Clock. 8 4 read-write USBS USB Input Clock Selection 0 1 read-write WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x504D43 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PWM Pulse Width Modulation Controller PWM 0x0 0x0 0x50 registers n PWM 36 CCNT0 PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT1 PWM Channel Counter Register (ch_num = 1) 0x234 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT2 PWM Channel Counter Register (ch_num = 2) 0x254 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT3 PWM Channel Counter Register (ch_num = 3) 0x274 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT4 PWM Channel Counter Register (ch_num = 4) 0x294 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT5 PWM Channel Counter Register (ch_num = 5) 0x2B4 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT6 PWM Channel Counter Register (ch_num = 6) 0x2D4 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT7 PWM Channel Counter Register (ch_num = 7) 0x2F4 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x224 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x244 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x264 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY4 PWM Channel Duty Cycle Register (ch_num = 4) 0x284 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY5 PWM Channel Duty Cycle Register (ch_num = 5) 0x2A4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY6 PWM Channel Duty Cycle Register (ch_num = 6) 0x2C4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY7 PWM Channel Duty Cycle Register (ch_num = 7) 0x2E4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD0 PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD1 PWM Channel Duty Cycle Update Register (ch_num = 1) 0x228 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD2 PWM Channel Duty Cycle Update Register (ch_num = 2) 0x248 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD3 PWM Channel Duty Cycle Update Register (ch_num = 3) 0x268 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD4 PWM Channel Duty Cycle Update Register (ch_num = 4) 0x288 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD5 PWM Channel Duty Cycle Update Register (ch_num = 5) 0x2A8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD6 PWM Channel Duty Cycle Update Register (ch_num = 6) 0x2C8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD7 PWM Channel Duty Cycle Update Register (ch_num = 7) 0x2E8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA, CLKB Divide Factor 0 8 read-write DIVB CLKA, CLKB Divide Factor 16 8 read-write PREA CLKA, CLKB Source Clock Selection 8 4 read-write PREB CLKA, CLKB Source Clock Selection 24 4 read-write CMPM0 PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM1 PWM Comparison 1 Mode Register 0x148 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM2 PWM Comparison 2 Mode Register 0x158 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM3 PWM Comparison 3 Mode Register 0x168 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM4 PWM Comparison 4 Mode Register 0x178 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM5 PWM Comparison 5 Mode Register 0x188 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM6 PWM Comparison 6 Mode Register 0x198 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM7 PWM Comparison 7 Mode Register 0x1A8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD0 PWM Comparison 0 Mode Update Register 0x13C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD1 PWM Comparison 1 Mode Update Register 0x14C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD2 PWM Comparison 2 Mode Update Register 0x15C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD3 PWM Comparison 3 Mode Update Register 0x16C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD4 PWM Comparison 4 Mode Update Register 0x17C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD5 PWM Comparison 5 Mode Update Register 0x18C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD6 PWM Comparison 6 Mode Update Register 0x19C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD7 PWM Comparison 7 Mode Update Register 0x1AC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV0 PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV1 PWM Comparison 1 Value Register 0x140 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV2 PWM Comparison 2 Value Register 0x150 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV3 PWM Comparison 3 Value Register 0x160 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV4 PWM Comparison 4 Value Register 0x170 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV5 PWM Comparison 5 Value Register 0x180 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV6 PWM Comparison 6 Value Register 0x190 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV7 PWM Comparison 7 Value Register 0x1A0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD0 PWM Comparison 0 Value Update Register 0x134 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD1 PWM Comparison 1 Value Update Register 0x144 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD2 PWM Comparison 2 Value Update Register 0x154 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD3 PWM Comparison 3 Value Update Register 0x164 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD4 PWM Comparison 4 Value Update Register 0x174 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD5 PWM Comparison 5 Value Update Register 0x184 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD6 PWM Comparison 6 Value Update Register 0x194 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD7 PWM Comparison 7 Value Update Register 0x1A4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR1 PWM Channel Mode Register (ch_num = 1) 0x220 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR2 PWM Channel Mode Register (ch_num = 2) 0x240 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR3 PWM Channel Mode Register (ch_num = 3) 0x260 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR4 PWM Channel Mode Register (ch_num = 4) 0x280 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR5 PWM Channel Mode Register (ch_num = 5) 0x2A0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR6 PWM Channel Mode Register (ch_num = 6) 0x2C0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CMR7 PWM Channel Mode Register (ch_num = 7) 0x2E0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CPRD0 PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD1 PWM Channel Period Register (ch_num = 1) 0x22C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD2 PWM Channel Period Register (ch_num = 2) 0x24C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD3 PWM Channel Period Register (ch_num = 3) 0x26C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD4 PWM Channel Period Register (ch_num = 4) 0x28C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD5 PWM Channel Period Register (ch_num = 5) 0x2AC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD6 PWM Channel Period Register (ch_num = 6) 0x2CC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD7 PWM Channel Period Register (ch_num = 7) 0x2EC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRDUPD0 PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD1 PWM Channel Period Update Register (ch_num = 1) 0x230 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD2 PWM Channel Period Update Register (ch_num = 2) 0x250 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD3 PWM Channel Period Update Register (ch_num = 3) 0x270 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD4 PWM Channel Period Update Register (ch_num = 4) 0x290 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD5 PWM Channel Period Update Register (ch_num = 5) 0x2B0 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD6 PWM Channel Period Update Register (ch_num = 6) 0x2D0 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD7 PWM Channel Period Update Register (ch_num = 7) 0x2F0 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only CHID4 Channel ID 4 1 write-only CHID5 Channel ID 5 1 write-only CHID6 Channel ID 6 1 write-only CHID7 Channel ID 7 1 write-only DT0 PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT1 PWM Channel Dead Time Register (ch_num = 1) 0x238 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT2 PWM Channel Dead Time Register (ch_num = 2) 0x258 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT3 PWM Channel Dead Time Register (ch_num = 3) 0x278 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT4 PWM Channel Dead Time Register (ch_num = 4) 0x298 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT5 PWM Channel Dead Time Register (ch_num = 5) 0x2B8 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT6 PWM Channel Dead Time Register (ch_num = 6) 0x2D8 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT7 PWM Channel Dead Time Register (ch_num = 7) 0x2F8 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD0 PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD1 PWM Channel Dead Time Update Register (ch_num = 1) 0x23C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD2 PWM Channel Dead Time Update Register (ch_num = 2) 0x25C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD3 PWM Channel Dead Time Update Register (ch_num = 3) 0x27C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD4 PWM Channel Dead Time Update Register (ch_num = 4) 0x29C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD5 PWM Channel Dead Time Update Register (ch_num = 5) 0x2BC 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD6 PWM Channel Dead Time Update Register (ch_num = 6) 0x2DC 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD7 PWM Channel Dead Time Update Register (ch_num = 7) 0x2FC 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only ELMR0 PWM Event Line 0 Mode Register 0x7C 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR1 PWM Event Line 0 Mode Register 0x80 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR[0] PWM Event Line 0 Mode Register 0xF8 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR[1] PWM Event Line 0 Mode Register 0x178 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only CHID4 Channel ID 4 1 write-only CHID5 Channel ID 5 1 write-only CHID6 Channel ID 6 1 write-only CHID7 Channel ID 7 1 write-only FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear (fault input bit varies from 0 to 5) 0 8 write-only FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering (fault input bit varies from 0 to 5) 16 8 read-write FMOD Fault Activation Mode (fault input bit varies from 0 to 5) 8 8 read-write FPOL Fault Polarity (fault input bit varies from 0 to 5) 0 8 read-write FPE1 PWM Fault Protection Enable Register 1 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) 0 8 read-write FPE1 Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) 8 8 read-write FPE2 Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) 16 8 read-write FPE3 Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) 24 8 read-write FPE2 PWM Fault Protection Enable Register 2 0x70 32 read-write n 0x0 0x0 FPE4 Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) 0 8 read-write FPE5 Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) 8 8 read-write FPE6 Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) 16 8 read-write FPE7 Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) 24 8 read-write FPV PWM Fault Protection Value Register 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 read-write FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 read-write FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 read-write FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 read-write FPVH4 Fault Protection Value for PWMH output on channel 4 4 1 read-write FPVH5 Fault Protection Value for PWMH output on channel 5 5 1 read-write FPVH6 Fault Protection Value for PWMH output on channel 6 6 1 read-write FPVH7 Fault Protection Value for PWMH output on channel 7 7 1 read-write FPVL0 Fault Protection Value for PWML output on channel 0 16 1 read-write FPVL1 Fault Protection Value for PWML output on channel 1 17 1 read-write FPVL2 Fault Protection Value for PWML output on channel 2 18 1 read-write FPVL3 Fault Protection Value for PWML output on channel 3 19 1 read-write FPVL4 Fault Protection Value for PWML output on channel 4 20 1 read-write FPVL5 Fault Protection Value for PWML output on channel 5 21 1 read-write FPVL6 Fault Protection Value for PWML output on channel 6 22 1 read-write FPVL7 Fault Protection Value for PWML output on channel 7 23 1 read-write FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value (fault input bit varies from 0 to 5) 0 8 read-only FS Fault Status (fault input bit varies from 0 to 5) 8 8 read-only IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 write-only CHID4 Counter Event on Channel 4 Interrupt Disable 4 1 write-only CHID5 Counter Event on Channel 5 Interrupt Disable 5 1 write-only CHID6 Counter Event on Channel 6 Interrupt Disable 6 1 write-only CHID7 Counter Event on Channel 7 Interrupt Disable 7 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 write-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Disable 20 1 write-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Disable 21 1 write-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Disable 22 1 write-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Disable 23 1 write-only IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Disable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Disable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Disable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Disable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Disable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Disable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Disable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Disable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Disable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Disable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Disable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Disable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Disable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Disable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Disable 23 1 write-only ENDTX PDC End of TX Buffer Interrupt Disable 1 1 write-only TXBUFE PDC TX Buffer Empty Interrupt Disable 2 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 write-only IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 write-only CHID4 Counter Event on Channel 4 Interrupt Enable 4 1 write-only CHID5 Counter Event on Channel 5 Interrupt Enable 5 1 write-only CHID6 Counter Event on Channel 6 Interrupt Enable 6 1 write-only CHID7 Counter Event on Channel 7 Interrupt Enable 7 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 write-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Enable 20 1 write-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Enable 21 1 write-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Enable 22 1 write-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Enable 23 1 write-only IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Enable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Enable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Enable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Enable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Enable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Enable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Enable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Enable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Enable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Enable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Enable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Enable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Enable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Enable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Enable 23 1 write-only ENDTX PDC End of TX Buffer Interrupt Enable 1 1 write-only TXBUFE PDC TX Buffer Empty Interrupt Enable 2 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 write-only IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 read-only CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 read-only CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 read-only CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 read-only CHID4 Counter Event on Channel 4 Interrupt Mask 4 1 read-only CHID5 Counter Event on Channel 5 Interrupt Mask 5 1 read-only CHID6 Counter Event on Channel 6 Interrupt Mask 6 1 read-only CHID7 Counter Event on Channel 7 Interrupt Mask 7 1 read-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 read-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Mask 20 1 read-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Mask 21 1 read-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Mask 22 1 read-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Mask 23 1 read-only IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 read-only CMPM1 Comparison 1 Match Interrupt Mask 9 1 read-only CMPM2 Comparison 2 Match Interrupt Mask 10 1 read-only CMPM3 Comparison 3 Match Interrupt Mask 11 1 read-only CMPM4 Comparison 4 Match Interrupt Mask 12 1 read-only CMPM5 Comparison 5 Match Interrupt Mask 13 1 read-only CMPM6 Comparison 6 Match Interrupt Mask 14 1 read-only CMPM7 Comparison 7 Match Interrupt Mask 15 1 read-only CMPU0 Comparison 0 Update Interrupt Mask 16 1 read-only CMPU1 Comparison 1 Update Interrupt Mask 17 1 read-only CMPU2 Comparison 2 Update Interrupt Mask 18 1 read-only CMPU3 Comparison 3 Update Interrupt Mask 19 1 read-only CMPU4 Comparison 4 Update Interrupt Mask 20 1 read-only CMPU5 Comparison 5 Update Interrupt Mask 21 1 read-only CMPU6 Comparison 6 Update Interrupt Mask 22 1 read-only CMPU7 Comparison 7 Update Interrupt Mask 23 1 read-only ENDTX PDC End of TX Buffer Interrupt Mask 1 1 read-only TXBUFE PDC TX Buffer Empty Interrupt Mask 2 1 read-only UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 read-only WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 read-only ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 read-only CHID1 Counter Event on Channel 1 1 1 read-only CHID2 Counter Event on Channel 2 2 1 read-only CHID3 Counter Event on Channel 3 3 1 read-only CHID4 Counter Event on Channel 4 4 1 read-only CHID5 Counter Event on Channel 5 5 1 read-only CHID6 Counter Event on Channel 6 6 1 read-only CHID7 Counter Event on Channel 7 7 1 read-only FCHID0 Fault Protection Trigger on Channel 0 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 19 1 read-only FCHID4 Fault Protection Trigger on Channel 4 20 1 read-only FCHID5 Fault Protection Trigger on Channel 5 21 1 read-only FCHID6 Fault Protection Trigger on Channel 6 22 1 read-only FCHID7 Fault Protection Trigger on Channel 7 23 1 read-only ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 read-only CMPM1 Comparison 1 Match 9 1 read-only CMPM2 Comparison 2 Match 10 1 read-only CMPM3 Comparison 3 Match 11 1 read-only CMPM4 Comparison 4 Match 12 1 read-only CMPM5 Comparison 5 Match 13 1 read-only CMPM6 Comparison 6 Match 14 1 read-only CMPM7 Comparison 7 Match 15 1 read-only CMPU0 Comparison 0 Update 16 1 read-only CMPU1 Comparison 1 Update 17 1 read-only CMPU2 Comparison 2 Update 18 1 read-only CMPU3 Comparison 3 Update 19 1 read-only CMPU4 Comparison 4 Update 20 1 read-only CMPU5 Comparison 5 Update 21 1 read-only CMPU6 Comparison 6 Update 22 1 read-only CMPU7 Comparison 7 Update 23 1 read-only ENDTX PDC End of TX Buffer 1 1 read-only TXBUFE PDC TX Buffer Empty 2 1 read-only UNRE Synchronous Channels Update Underrun Error 3 1 read-only WRDY Write Ready for Synchronous Channels Update 0 1 read-only OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 read-write OOVH1 Output Override Value for PWMH output of the channel 1 1 1 read-write OOVH2 Output Override Value for PWMH output of the channel 2 2 1 read-write OOVH3 Output Override Value for PWMH output of the channel 3 3 1 read-write OOVH4 Output Override Value for PWMH output of the channel 4 4 1 read-write OOVH5 Output Override Value for PWMH output of the channel 5 5 1 read-write OOVH6 Output Override Value for PWMH output of the channel 6 6 1 read-write OOVH7 Output Override Value for PWMH output of the channel 7 7 1 read-write OOVL0 Output Override Value for PWML output of the channel 0 16 1 read-write OOVL1 Output Override Value for PWML output of the channel 1 17 1 read-write OOVL2 Output Override Value for PWML output of the channel 2 18 1 read-write OOVL3 Output Override Value for PWML output of the channel 3 19 1 read-write OOVL4 Output Override Value for PWML output of the channel 4 20 1 read-write OOVL5 Output Override Value for PWML output of the channel 5 21 1 read-write OOVL6 Output Override Value for PWML output of the channel 6 22 1 read-write OOVL7 Output Override Value for PWML output of the channel 7 23 1 read-write OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 read-write OSH1 Output Selection for PWMH output of the channel 1 1 1 read-write OSH2 Output Selection for PWMH output of the channel 2 2 1 read-write OSH3 Output Selection for PWMH output of the channel 3 3 1 read-write OSH4 Output Selection for PWMH output of the channel 4 4 1 read-write OSH5 Output Selection for PWMH output of the channel 5 5 1 read-write OSH6 Output Selection for PWMH output of the channel 6 6 1 read-write OSH7 Output Selection for PWMH output of the channel 7 7 1 read-write OSL0 Output Selection for PWML output of the channel 0 16 1 read-write OSL1 Output Selection for PWML output of the channel 1 17 1 read-write OSL2 Output Selection for PWML output of the channel 2 18 1 read-write OSL3 Output Selection for PWML output of the channel 3 19 1 read-write OSL4 Output Selection for PWML output of the channel 4 20 1 read-write OSL5 Output Selection for PWML output of the channel 5 21 1 read-write OSL6 Output Selection for PWML output of the channel 6 22 1 read-write OSL7 Output Selection for PWML output of the channel 7 23 1 read-write OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCH4 Output Selection Clear for PWMH output of the channel 4 4 1 write-only OSCH5 Output Selection Clear for PWMH output of the channel 5 5 1 write-only OSCH6 Output Selection Clear for PWMH output of the channel 6 6 1 write-only OSCH7 Output Selection Clear for PWMH output of the channel 7 7 1 write-only OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCL4 Output Selection Clear for PWML output of the channel 4 20 1 write-only OSCL5 Output Selection Clear for PWML output of the channel 5 21 1 write-only OSCL6 Output Selection Clear for PWML output of the channel 6 22 1 write-only OSCL7 Output Selection Clear for PWML output of the channel 7 23 1 write-only OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCUPH4 Output Selection Clear for PWMH output of the channel 4 4 1 write-only OSCUPH5 Output Selection Clear for PWMH output of the channel 5 5 1 write-only OSCUPH6 Output Selection Clear for PWMH output of the channel 6 6 1 write-only OSCUPH7 Output Selection Clear for PWMH output of the channel 7 7 1 write-only OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCUPL4 Output Selection Clear for PWML output of the channel 4 20 1 write-only OSCUPL5 Output Selection Clear for PWML output of the channel 5 21 1 write-only OSCUPL6 Output Selection Clear for PWML output of the channel 6 22 1 write-only OSCUPL7 Output Selection Clear for PWML output of the channel 7 23 1 write-only OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSH4 Output Selection Set for PWMH output of the channel 4 4 1 write-only OSSH5 Output Selection Set for PWMH output of the channel 5 5 1 write-only OSSH6 Output Selection Set for PWMH output of the channel 6 6 1 write-only OSSH7 Output Selection Set for PWMH output of the channel 7 7 1 write-only OSSL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSL4 Output Selection Set for PWML output of the channel 4 20 1 write-only OSSL5 Output Selection Set for PWML output of the channel 5 21 1 write-only OSSL6 Output Selection Set for PWML output of the channel 6 22 1 write-only OSSL7 Output Selection Set for PWML output of the channel 7 23 1 write-only OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSUPH4 Output Selection Set for PWMH output of the channel 4 4 1 write-only OSSUPH5 Output Selection Set for PWMH output of the channel 5 5 1 write-only OSSUPH6 Output Selection Set for PWMH output of the channel 6 6 1 write-only OSSUPH7 Output Selection Set for PWMH output of the channel 7 7 1 write-only OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSUPL4 Output Selection Set for PWML output of the channel 4 20 1 write-only OSSUPL5 Output Selection Set for PWML output of the channel 5 21 1 write-only OSSUPL6 Output Selection Set for PWML output of the channel 6 22 1 write-only OSSUPL7 Output Selection Set for PWML output of the channel 7 23 1 write-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS PDC Transfer Request Comparison Selection 21 3 read-write PTRM PDC Transfer Request Mode 20 1 read-write SYNC0 Synchronous Channel 0 0 1 read-write SYNC1 Synchronous Channel 1 1 1 read-write SYNC2 Synchronous Channel 2 2 1 read-write SYNC3 Synchronous Channel 3 3 1 read-write SYNC4 Synchronous Channel 4 4 1 read-write SYNC5 Synchronous Channel 5 5 1 read-write SYNC6 Synchronous Channel 6 6 1 read-write SYNC7 Synchronous Channel 7 7 1 read-write UPDM Synchronous Channels Update Mode 16 2 read-write MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels 0x2 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 read-write SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 read-write UPRCNT Update Period Counter 4 4 read-write SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 write-only SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 read-write DOWN1 DOWN Count 17 1 read-write DOWN2 DOWN Count 18 1 read-write DOWN3 DOWN Count 19 1 read-write GCEN0 Gray Count ENable 0 1 read-write GCEN1 Gray Count ENable 1 1 read-write GCEN2 Gray Count ENable 2 1 read-write GCEN3 Gray Count ENable 3 1 read-write SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only CHID4 Channel ID 4 1 read-only CHID5 Channel ID 5 1 read-only CHID6 Channel ID 6 1 read-only CHID7 Channel ID 7 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPCR PWM Write Protect Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protect Command 0 2 write-only WPKEY Write Protect Key 8 24 write-only WPRG0 Write Protect Register Group 0 2 1 write-only WPRG1 Write Protect Register Group 1 3 1 write-only WPRG2 Write Protect Register Group 2 4 1 write-only WPRG3 Write Protect Register Group 3 5 1 write-only WPRG4 Write Protect Register Group 4 6 1 write-only WPRG5 Write Protect Register Group 5 7 1 write-only WPSR PWM Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 read-only WPHWS1 Write Protect HW Status 9 1 read-only WPHWS2 Write Protect HW Status 10 1 read-only WPHWS3 Write Protect HW Status 11 1 read-only WPHWS4 Write Protect HW Status 12 1 read-only WPHWS5 Write Protect HW Status 13 1 read-only WPSWS0 Write Protect SW Status 0 1 read-only WPSWS1 Write Protect SW Status 1 1 read-only WPSWS2 Write Protect SW Status 2 1 read-only WPSWS3 Write Protect SW Status 3 1 read-only WPSWS4 Write Protect SW Status 4 1 read-only WPSWS5 Write Protect SW Status 5 1 read-only WPVS Write Protect Violation Status 7 1 read-only WPVSRC Write Protect Violation Source 16 16 read-only RSTC Reset Controller SYSC 0x0 0x0 0x10 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 EXTRST External Reset 3 1 write-only KEY System Reset Key 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 PERRST Peripheral Reset 2 1 write-only PROCRST Processor Reset 0 1 write-only MR Mode Register 0x8 32 read-write n 0x0 0x0 ERSTL External Reset Length 8 4 read-write KEY Write Access Password 24 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 URSTEN User Reset Enable 0 1 read-write URSTIEN User Reset Interrupt Enable 4 1 read-write SR Status Register 0x4 32 read-only n 0x0 0x0 NRSTL NRST Pin Level 16 1 read-only RSTTYP Reset Type 8 3 read-only GeneralReset First power-up Reset 0x0 BackupReset Return from Backup Mode 0x1 WatchdogReset Watchdog fault occurred 0x2 SoftwareReset Processor reset required by the software 0x3 UserReset NRST pin detected low 0x4 SRCMP Software Reset Command in Progress 17 1 read-only URSTS User Reset Status 0 1 read-only RTC Real-time Clock SYSC 0x0 0x0 0xE8 registers n CALALR Calendar Alarm Register 0x14 32 read-write n 0x0 0x0 DATE Date Alarm 24 6 read-write DATEEN Date Alarm Enable 31 1 read-write MONTH Month Alarm 16 5 read-write MTHEN Month Alarm Enable 23 1 read-write CALR Calendar Register 0xC 32 read-write n 0x0 0x0 CENT Current Century 0 7 read-write DATE Current Day in Current Month 24 6 read-write DAY Current Day in Current Week 21 3 read-write MONTH Current Month 16 5 read-write YEAR Current Year 8 8 read-write CR Control Register 0x0 32 read-write n 0x0 0x0 CALEVSEL Calendar Event Selection 16 2 read-write WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 TIMEVSEL Time Event Selection 8 2 read-write MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 UPDCAL Update Request Calendar Register 1 1 read-write UPDTIM Update Request Time Register 0 1 read-write IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ACKDIS Acknowledge Update Interrupt Disable 0 1 write-only ALRDIS Alarm Interrupt Disable 1 1 write-only CALDIS Calendar Event Interrupt Disable 4 1 write-only SECDIS Second Event Interrupt Disable 2 1 write-only TIMDIS Time Event Interrupt Disable 3 1 write-only IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ACKEN Acknowledge Update Interrupt Enable 0 1 write-only ALREN Alarm Interrupt Enable 1 1 write-only CALEN Calendar Event Interrupt Enable 4 1 write-only SECEN Second Event Interrupt Enable 2 1 write-only TIMEN Time Event Interrupt Enable 3 1 write-only IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ACK Acknowledge Update Interrupt Mask 0 1 read-only ALR Alarm Interrupt Mask 1 1 read-only CAL Calendar Event Interrupt Mask 4 1 read-only SEC Second Event Interrupt Mask 2 1 read-only TIM Time Event Interrupt Mask 3 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 HRMOD 12-/24-hour Mode 0 1 read-write SCCR Status Clear Command Register 0x1C 32 write-only n 0x0 0x0 ACKCLR Acknowledge Clear 0 1 write-only ALRCLR Alarm Clear 1 1 write-only CALCLR Calendar Clear 4 1 write-only SECCLR Second Clear 2 1 write-only TIMCLR Time Clear 3 1 write-only SR Status Register 0x18 32 read-only n 0x0 0x0 ACKUPD Acknowledge for Update 0 1 read-only FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 read-only NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 CALEV Calendar Event 4 1 read-only NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SEC Second Event 2 1 read-only NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TIMEV Time Event 3 1 read-only NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 TIMALR Time Alarm Register 0x10 32 read-write n 0x0 0x0 AMPM AM/PM Indicator 22 1 read-write HOUR Hour Alarm 16 6 read-write HOUREN Hour Alarm Enable 23 1 read-write MIN Minute Alarm 8 7 read-write MINEN Minute Alarm Enable 15 1 read-write SEC Second Alarm 0 7 read-write SECEN Second Alarm Enable 7 1 read-write TIMR Time Register 0x8 32 read-write n 0x0 0x0 AMPM Ante Meridiem Post Meridiem Indicator 22 1 read-write HOUR Current Hour 16 6 read-write MIN Current Minute 8 7 read-write SEC Current Second 0 7 read-write VER Valid Entry Register 0x2C 32 read-only n 0x0 0x0 NVCAL Non-valid Calendar 1 1 read-only NVCALALR Non-valid Calendar Alarm 3 1 read-only NVTIM Non-valid Time 0 1 read-only NVTIMALR Non-valid Time Alarm 2 1 read-only WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x525443 RTT Real-time Timer SYSC 0x0 0x0 0x10 registers n AR Alarm Register 0x4 32 read-write n 0x0 0x0 ALMV Alarm Value 0 32 read-write MR Mode Register 0x0 32 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable 16 1 read-write RTPRES Real-time Timer Prescaler Value 0 16 read-write RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 read-write RTTRST Real-time Timer Restart 18 1 read-write SR Status Register 0xC 32 read-only n 0x0 0x0 ALMS Real-time Alarm Status 0 1 read-only RTTINC Real-time Timer Increment 1 1 read-only VR Value Register 0x8 32 read-only n 0x0 0x0 CRTV Current Real-time Value 0 32 read-only SMC Static Memory Controller EBI 0x0 0x0 0x200 registers n ADDR SMC NFC Address Cycle Zero Register 0x18 32 read-write n 0x0 0x0 ADDR_CYCLE0 NAND Flash Array Address cycle 0 0 8 read-write BANK SMC Bank Address Register 0x1C 32 read-write n 0x0 0x0 BANK Bank Identifier 0 3 read-write CFG SMC NFC Configuration Register 0x0 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 16 4 read-write DTOMUL Data Timeout Multiplier 20 3 read-write X1 DTOCYC 0x0 X16 DTOCYC x 16 0x1 X128 DTOCYC x 128 0x2 X256 DTOCYC x 256 0x3 X1024 DTOCYC x 1024 0x4 X4096 DTOCYC x 4096 0x5 X65536 DTOCYC x 65536 0x6 X1048576 DTOCYC x 1048576 0x7 EDGECTRL Rising/Falling Edge Detection Control 12 1 read-write PAGESIZE Page Size of the NAND Flash Device 0 2 read-write PS512 Main area 512 Bytes 0x0 PS1024 Main area 1024 Bytes 0x1 PS2048 Main area 2048 Bytes 0x2 PS4096 Main area 4096 Bytes 0x3 RBEDGE Ready/Busy Signal Edge Detection 13 1 read-write RSPARE Read Spare Area 9 1 read-write WSPARE Write Spare Area 8 1 read-write CTRL SMC NFC Control Register 0x4 32 write-only n 0x0 0x0 NFCDIS NAND Flash Controller Disable 1 1 write-only NFCEN NAND Flash Controller Enable 0 1 write-only CYCLE0 SMC Cycle Register (CS_number = 0) 0x78 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE1 SMC Cycle Register (CS_number = 1) 0x8C 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE2 SMC Cycle Register (CS_number = 2) 0xA0 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE3 SMC Cycle Register (CS_number = 3) 0xB4 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE4 SMC Cycle Register (CS_number = 4) 0xC8 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE5 SMC Cycle Register (CS_number = 5) 0xDC 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE6 SMC Cycle Register (CS_number = 6) 0xF0 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE7 SMC Cycle Register (CS_number = 7) 0x104 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write ECC_CTRL SMC ECC Control Register 0x20 32 write-only n 0x0 0x0 RST Reset ECC 0 1 write-only SWRST Software Reset 1 1 write-only ECC_MD SMC ECC Mode Register 0x24 32 read-write n 0x0 0x0 ECC_PAGESIZE ECC Page Size 0 2 read-write PS512 Main area 512 Words 0x0 PS1024 Main area 1024 Words 0x1 PS2048 Main area 2048 Words 0x2 PS4096 Main area 4096 Words 0x3 TYPCORREC Type of Correction 4 2 read-write CPAGE 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) 0x0 C256B 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) 0x1 C512B 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) 0x2 ECC_PR0 SMC ECC Parity 0 Register 0x2C 32 read-only n 0x0 0x0 BITADDR Bit Address 0 4 read-only WORDADDR Word Address 4 12 read-only ECC_PR0_W8BIT SMC ECC Parity 0 Register W8BIT 0x2C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR0_W9BIT SMC ECC Parity 0 Register W9BIT 0x2C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR1 SMC ECC parity 1 Register 0x30 32 read-only n 0x0 0x0 NPARITY Parity N 0 16 read-only ECC_PR10 SMC ECC parity 10 Register 0x58 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR11 SMC ECC parity 11 Register 0x5C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR12 SMC ECC parity 12 Register 0x60 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR13 SMC ECC parity 13 Register 0x64 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR14 SMC ECC parity 14 Register 0x68 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR15 SMC ECC parity 15 Register 0x6C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR1_W8BIT SMC ECC parity 1 Register W8BIT 0x30 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR1_W9BIT SMC ECC parity 1 Register W9BIT 0x30 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR2 SMC ECC parity 2 Register 0x38 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR2_W8BIT SMC ECC parity 2 Register W8BIT 0x38 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR3 SMC ECC parity 3 Register 0x3C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR3_W8BIT SMC ECC parity 3 Register W8BIT 0x3C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR4 SMC ECC parity 4 Register 0x40 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR4_W8BIT SMC ECC parity 4 Register W8BIT 0x40 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR5 SMC ECC parity 5 Register 0x44 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR5_W8BIT SMC ECC parity 5 Register W8BIT 0x44 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR6 SMC ECC parity 6 Register 0x48 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR6_W8BIT SMC ECC parity 6 Register W8BIT 0x48 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR7 SMC ECC parity 7 Register 0x4C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 12 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only ECC_PR7_W8BIT SMC ECC parity 7 Register W8BIT 0x4C 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR8 SMC ECC parity 8 Register 0x50 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_PR9 SMC ECC parity 9 Register 0x54 32 read-only n 0x0 0x0 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only NPARITY Parity N 12 11 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only ECC_SR1 SMC ECC Status 1 Register 0x28 32 read-only n 0x0 0x0 ECCERR0 ECC Error 1 1 read-only ECCERR1 ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes 5 1 read-only ECCERR2 ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 9 1 read-only ECCERR3 ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 13 1 read-only ECCERR4 ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 17 1 read-only ECCERR5 ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 21 1 read-only ECCERR6 ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 25 1 read-only ECCERR7 ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 29 1 read-only MULERR0 Multiple Error 2 1 read-only MULERR1 Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes 6 1 read-only MULERR2 Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 10 1 read-only MULERR3 Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 14 1 read-only MULERR4 Multiple Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 18 1 read-only MULERR5 Multiple Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 22 1 read-only MULERR6 Multiple Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 26 1 read-only MULERR7 Multiple Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 30 1 read-only RECERR0 Recoverable Error 0 1 read-only RECERR1 Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes 4 1 read-only RECERR2 Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 8 1 read-only RECERR3 Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 12 1 read-only RECERR4 Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 16 1 read-only RECERR5 Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 20 1 read-only RECERR6 Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 24 1 read-only RECERR7 Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 28 1 read-only ECC_SR2 SMC ECC status 2 Register 0x34 32 read-only n 0x0 0x0 ECCERR10 ECC Error in the page between the 2560th and the 2815th bytes 9 1 read-only ECCERR11 ECC Error in the page between the 2816th and the 3071st bytes 13 1 read-only ECCERR12 ECC Error in the page between the 3072nd and the 3327th bytes 17 1 read-only ECCERR13 ECC Error in the page between the 3328th and the 3583rd bytes 21 1 read-only ECCERR14 ECC Error in the page between the 3584th and the 3839th bytes 25 1 read-only ECCERR15 ECC Error in the page between the 3840th and the 4095th bytes 29 1 read-only ECCERR8 ECC Error in the page between the 2048th and the 2303rd bytes 1 1 read-only ECCERR9 ECC Error in the page between the 2304th and the 2559th bytes 5 1 read-only MULERR10 Multiple Error in the page between the 2560th and the 2815th bytes 10 1 read-only MULERR11 Multiple Error in the page between the 2816th and the 3071st bytes 14 1 read-only MULERR12 Multiple Error in the page between the 3072nd and the 3327th bytes 18 1 read-only MULERR13 Multiple Error in the page between the 3328th and the 3583rd bytes 22 1 read-only MULERR14 Multiple Error in the page between the 3584th and the 3839th bytes 26 1 read-only MULERR15 Multiple Error in the page between the 3840th and the 4095th bytes 30 1 read-only MULERR8 Multiple Error in the page between the 2048th and the 2303rd bytes 2 1 read-only MULERR9 Multiple Error in the page between the 2304th and the 2559th bytes 6 1 read-only RECERR10 Recoverable Error in the page between the 2560th and the 2815th bytes 8 1 read-only RECERR11 Recoverable Error in the page between the 2816th and the 3071st bytes 12 1 read-only RECERR12 Recoverable Error in the page between the 3072nd and the 3327th bytes 16 1 read-only RECERR13 Recoverable Error in the page between the 3328th and the 3583rd bytes 20 1 read-only RECERR14 Recoverable Error in the page between the 3584th and the 3839th bytes 24 1 read-only RECERR15 Recoverable Error in the page between the 3840th and the 4095th bytes 28 1 read-only RECERR8 Recoverable Error in the page between the 2048th and the 2303rd bytes 0 1 read-only RECERR9 Recoverable Error in the page between the 2304th and the 2559th bytes 4 1 read-only IDR SMC NFC Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 AWB Accessing While Busy Interrupt Disable 22 1 write-only CMDDONE Command Done Interrupt Disable 17 1 write-only DTOE Data Timeout Error Interrupt Disable 20 1 write-only NFCASE NFC Access Size Error Interrupt Disable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Disable 24 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Disable 5 1 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Disable 4 1 write-only UNDEF Undefined Area Access Interrupt Disable 21 1 write-only XFRDONE Transfer Done Interrupt Disable 16 1 write-only IER SMC NFC Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 AWB Accessing While Busy Interrupt Enable 22 1 write-only CMDDONE Command Done Interrupt Enable 17 1 write-only DTOE Data Timeout Error Interrupt Enable 20 1 write-only NFCASE NFC Access Size Error Interrupt Enable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Enable 24 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Enable 5 1 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Enable 4 1 write-only UNDEF Undefined Area Access Interrupt Enable 21 1 write-only XFRDONE Transfer Done Interrupt Enable 16 1 write-only IMR SMC NFC Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 AWB Accessing While Busy Interrupt Mask 22 1 read-only CMDDONE Command Done Interrupt Mask 17 1 read-only DTOE Data Timeout Error Interrupt Mask 20 1 read-only NFCASE NFC Access Size Error Interrupt Mask 23 1 read-only RB_EDGE0 Ready/Busy Line 0 Interrupt Mask 24 1 read-only RB_FALL Ready Busy Falling Edge Detection Interrupt Mask 5 1 read-only RB_RISE Ready Busy Rising Edge Detection Interrupt Mask 4 1 read-only UNDEF Undefined Area Access Interrupt Mask5 21 1 read-only XFRDONE Transfer Done Interrupt Mask 16 1 read-only KEY1 SMC OCMS KEY1 Register 0x114 32 write-only n 0x0 0x0 KEY1 Off Chip Memory Scrambling (OCMS) Key Part 1 0 32 write-only KEY2 SMC OCMS KEY2 Register 0x118 32 write-only n 0x0 0x0 KEY2 Off Chip Memory Scrambling (OCMS) Key Part 2 0 32 write-only MODE0 SMC Mode Register (CS_number = 0) 0x80 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE1 SMC Mode Register (CS_number = 1) 0x94 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE2 SMC Mode Register (CS_number = 2) 0xA8 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE3 SMC Mode Register (CS_number = 3) 0xBC 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE4 SMC Mode Register (CS_number = 4) 0xD0 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE5 SMC Mode Register (CS_number = 5) 0xE4 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE6 SMC Mode Register (CS_number = 6) 0xF8 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 MODE7 SMC Mode Register (CS_number = 7) 0x10C 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 OCMS SMC OCMS Register 0x110 32 read-write n 0x0 0x0 SMSE Static Memory Controller Scrambling Enable 0 1 read-write SRSE SRAM Scrambling Enable 1 1 read-write PULSE0 SMC Pulse Register (CS_number = 0) 0x74 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE1 SMC Pulse Register (CS_number = 1) 0x88 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE2 SMC Pulse Register (CS_number = 2) 0x9C 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE3 SMC Pulse Register (CS_number = 3) 0xB0 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE4 SMC Pulse Register (CS_number = 4) 0xC4 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE5 SMC Pulse Register (CS_number = 5) 0xD8 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE6 SMC Pulse Register (CS_number = 6) 0xEC 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE7 SMC Pulse Register (CS_number = 7) 0x100 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write SETUP0 SMC Setup Register (CS_number = 0) 0x70 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP1 SMC Setup Register (CS_number = 1) 0x84 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP2 SMC Setup Register (CS_number = 2) 0x98 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP3 SMC Setup Register (CS_number = 3) 0xAC 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP4 SMC Setup Register (CS_number = 4) 0xC0 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP5 SMC Setup Register (CS_number = 5) 0xD4 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP6 SMC Setup Register (CS_number = 6) 0xE8 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP7 SMC Setup Register (CS_number = 7) 0xFC 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SR SMC NFC Status Register 0x8 32 read-only n 0x0 0x0 AWB Accessing While Busy 22 1 read-only CMDDONE Command Done 17 1 read-only DTOE Data Timeout Error 20 1 read-only NFCASE NFC Access Size Error 23 1 read-only NFCBUSY NFC Busy (this field cannot be reset) 8 1 read-only NFCSID NFC Chip Select ID (this field cannot be reset) 12 3 read-only NFCWR NFC Write/Read Operation (this field cannot be reset) 11 1 read-only RB_EDGE0 Ready/Busy Line 0 Edge Detected 24 1 read-only RB_FALL Selected Ready Busy Falling Edge Detected 5 1 read-only RB_RISE Selected Ready Busy Rising Edge Detected 4 1 read-only SMCSTS NAND Flash Controller status (this field cannot be reset) 0 1 read-only UNDEF Undefined Area Error 21 1 read-only XFRDONE NFC Data Transfer Terminated 16 1 read-only TIMINGS0 SMC Timings Register (CS_number = 0) 0x7C 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS1 SMC Timings Register (CS_number = 1) 0x90 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS2 SMC Timings Register (CS_number = 2) 0xA4 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS3 SMC Timings Register (CS_number = 3) 0xB8 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS4 SMC Timings Register (CS_number = 4) 0xCC 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS5 SMC Timings Register (CS_number = 5) 0xE0 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS6 SMC Timings Register (CS_number = 6) 0xF4 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS7 SMC Timings Register (CS_number = 7) 0x108 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write WPCR Write Protection Control Register 0x1E4 32 write-only n 0x0 0x0 WP_EN Write Protection Enable 0 1 write-only WP_KEY Write Protection KEY Password 8 24 write-only PASSWD Writing any other value in this field aborts the write operation of the WP_EN bit. Always reads as 0. 0x534D43 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WP_VS Write Protection Violation Status 0 4 read-only WP_VSRC Write Protection Violation Source 8 16 read-only SPI0 Serial Peripheral Interface 0 SPI 0x0 0x0 0x50 registers n SPI0 24 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR1 Chip Select Register 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR2 Chip Select Register 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR3 Chip Select Register 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[0] Chip Select Register 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[1] Chip Select Register 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[2] Chip Select Register 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[3] Chip Select Register 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 MODF Mode Fault Error 2 1 read-only NSSR NSS Rising 8 1 read-only OVRES Overrun Error Status 3 1 read-only RDRF Receive Data Register Full 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty 1 1 read-only TXEMPTY Transmission Registers Empty 9 1 read-only UNDES Underrun Error Status (Slave Mode Only) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Control Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SSC Synchronous Serial Controller SSC 0x0 0x0 0x50 registers n SSC 26 CMR Clock Mode Register 0x4 32 read-write n 0x0 0x0 DIV Clock Divider 0 12 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RXDIS Receive Disable 1 1 write-only RXEN Receive Enable 0 1 write-only SWRST Software Reset 15 1 write-only TXDIS Transmit Disable 9 1 write-only TXEN Transmit Enable 8 1 write-only IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RC0R Receive Compare 0 Register 0x38 32 read-write n 0x0 0x0 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x3C 32 read-write n 0x0 0x0 CP1 Receive Compare Data 1 0 16 read-write RCMR Receive Clock Mode Register 0x10 32 read-write n 0x0 0x0 CKG Receive Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_RF_LOW Receive Clock enabled only if RF Low 0x1 EN_RF_HIGH Receive Clock enabled only if RF High 0x2 CKI Receive Clock Inversion 5 1 read-write CKO Receive Clock Output Mode Selection 2 3 read-write NONE None, RK pin is an input 0x0 CONTINUOUS Continuous Receive Clock, RK pin is an output 0x1 TRANSFER Receive Clock only during data transfers, RK pin is an output 0x2 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 PERIOD Receive Period Divider Selection 24 8 read-write START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write RFMR Receive Frame Mode Register 0x14 32 read-write n 0x0 0x0 DATLEN Data Length 0 5 read-write DATNB Data Number per Frame 8 4 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Receive Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer, RF pin is an output 0x3 HIGH Driven High during data transfer, RF pin is an output 0x4 TOGGLING Toggling at each start of data transfer, RF pin is an output 0x5 LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 read-only RSHR Receive Sync. Holding Register 0x30 32 read-only n 0x0 0x0 RSDAT Receive Synchronization Data 0 16 read-only SR Status Register 0x40 32 read-only n 0x0 0x0 CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only OVRUN Receive Overrun 5 1 read-only RXEN Receive Enable 17 1 read-only RXRDY Receive Ready 4 1 read-only RXSYN Receive Sync 11 1 read-only TXEMPTY Transmit Empty 1 1 read-only TXEN Transmit Enable 16 1 read-only TXRDY Transmit Ready 0 1 read-only TXSYN Transmit Sync 10 1 read-only TCMR Transmit Clock Mode Register 0x18 32 read-write n 0x0 0x0 CKG Transmit Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_TF_LOW Transmit Clock enabled only if TF Low 0x1 EN_TF_HIGH Transmit Clock enabled only if TF High 0x2 CKI Transmit Clock Inversion 5 1 read-write CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None, TK pin is an input 0x0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 0x1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 0x2 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 RK RK Clock signal 0x1 TK TK pin 0x2 PERIOD Transmit Period Divider Selection 24 8 read-write START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data 0x0 RECEIVE Receive start 0x1 TF_LOW Detection of a low level on TF signal 0x2 TF_HIGH Detection of a high level on TF signal 0x3 TF_FALLING Detection of a falling edge on TF signal 0x4 TF_RISING Detection of a rising edge on TF signal 0x5 TF_LEVEL Detection of any level change on TF signal 0x6 TF_EDGE Detection of any edge on TF signal 0x7 STTDLY Transmit Start Delay 16 8 read-write TFMR Transmit Frame Mode Register 0x1C 32 read-write n 0x0 0x0 DATDEF Data Default Value 5 1 read-write DATLEN Data Length 0 5 read-write DATNB Data Number per frame 8 4 read-write FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Transmit Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 MSBF Most Significant Bit First 7 1 read-write THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 write-only TSHR Transmit Sync. Holding Register 0x34 32 read-write n 0x0 0x0 TSDAT Transmit Synchronization Data 0 16 read-write WPMR Write Protect Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535343 WPSR Write Protect Status Register 0xE8 32 read-only n 0x0 0x0 SUPC Supply Controller SYSC 0x0 0x0 0x18 registers n CR Supply Controller Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 VROFF Voltage Regulator Off 2 1 write-only NO_EFFECT no effect. 0 STOP_VREG if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. 1 XTALSEL Crystal Oscillator Select 3 1 write-only NO_EFFECT no effect. 0 CRYSTAL_SEL if KEY is correct, switches the slow clock on the crystal oscillator output. 1 MR Supply Controller Mode Register 0x8 32 read-write n 0x0 0x0 BODDIS Brownout Detector Disable 13 1 read-write ENABLE the core brownout detector is enabled. 0 DISABLE the core brownout detector is disabled. 1 BODRSTEN Brownout Detector Reset Enable 12 1 read-write NOT_ENABLE the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. 0 ENABLE the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 1 KEY Password Key 24 8 read-write PASSWD Writing any other value in this field aborts the write operation. 0xA5 OSCBYPASS Oscillator Bypass 20 1 read-write NO_EFFECT no effect. Clock selection depends on XTALSEL value. 0 BYPASS the 32-KHz XTAL oscillator is selected and is put in bypass mode. 1 VDDIORDY VDDIO Ready 14 1 read-write VDDIO_REMOVED VDDIO is removed (used before going to backup mode when backup batteries are used) 0 VDDIO_PRESENT VDDIO is present (used before going to backup mode when backup batteries are used) 1 SMMR Supply Controller Supply Monitor Mode Register 0x4 32 read-write n 0x0 0x0 SMIEN Supply Monitor Interrupt Enable 13 1 read-write NOT_ENABLE the SUPC interrupt signal is not affected when a supply monitor detection occurs. 0 ENABLE the SUPC interrupt signal is asserted when a supply monitor detection occurs. 1 SMRSTEN Supply Monitor Reset Enable 12 1 read-write NOT_ENABLE the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. 0 ENABLE the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 1 SMSMPL Supply Monitor Sampling Period 8 3 read-write SMD Supply Monitor disabled 0x0 CSM Continuous Supply Monitor 0x1 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x2 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x3 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x4 SMTH Supply Monitor Threshold 0 4 read-write SR Supply Controller Status Register 0x14 32 read-only n 0x0 0x0 BODRSTS Brownout Detector Reset Status 3 1 read-only NO no core brownout rising edge event has been detected since the last read of the SUPC_SR. 0 PRESENT at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. 1 FWUPIS FWUP Input Status 12 1 read-only LOW FWUP input is tied low. 0 HIGH FWUP input is tied high. 1 FWUPS FWUP Wake-up Status 0 1 read-only NO no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 1 OSCSEL 32-kHz Oscillator Selection Status 7 1 read-only RC the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 0 CRYST the slow clock, SLCK is generated by the 32-kHz crystal oscillator. 1 SMOS Supply Monitor Output Status 6 1 read-only HIGH the supply monitor detected VDDUTMI higher than its threshold at its last measurement. 0 LOW the supply monitor detected VDDUTMI lower than its threshold at its last measurement. 1 SMRSTS Supply Monitor Reset Status 4 1 read-only NO no supply monitor detection has generated a core reset since the last read of the SUPC_SR. 0 PRESENT at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 SMS Supply Monitor Status 5 1 read-only NO no supply monitor detection since the last read of SUPC_SR. 0 PRESENT at least one supply monitor detection since the last read of SUPC_SR. 1 SMWS Supply Monitor Detection Wake-up Status 2 1 read-only NO no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 WKUPIS0 WKUP Input Status 0 16 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS1 WKUP Input Status 1 17 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS10 WKUP Input Status 10 26 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS11 WKUP Input Status 11 27 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS12 WKUP Input Status 12 28 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS13 WKUP Input Status 13 29 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS14 WKUP Input Status 14 30 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS15 WKUP Input Status 15 31 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS2 WKUP Input Status 2 18 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS3 WKUP Input Status 3 19 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS4 WKUP Input Status 4 20 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS5 WKUP Input Status 5 21 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS6 WKUP Input Status 6 22 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS7 WKUP Input Status 7 23 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS8 WKUP Input Status 8 24 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS9 WKUP Input Status 9 25 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPS WKUP Wake-up Status 1 1 read-only NO no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 WUIR Supply Controller Wake-up Inputs Register 0x10 32 read-write n 0x0 0x0 WKUPEN0 Wake-up Input Enable 0 0 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN1 Wake-up Input Enable 1 1 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN10 Wake-up Input Enable 10 10 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN11 Wake-up Input Enable 11 11 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN12 Wake-up Input Enable 12 12 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN13 Wake-up Input Enable 13 13 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN14 Wake-up Input Enable 14 14 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN15 Wake-up Input Enable 15 15 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN2 Wake-up Input Enable 2 2 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN3 Wake-up Input Enable 3 3 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN4 Wake-up Input Enable 4 4 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN5 Wake-up Input Enable 5 5 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN6 Wake-up Input Enable 6 6 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN7 Wake-up Input Enable 7 7 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN8 Wake-up Input Enable 8 8 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN9 Wake-up Input Enable 9 9 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT0 Wake-up Input Type 0 16 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT1 Wake-up Input Type 1 17 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT10 Wake-up Input Type 10 26 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT11 Wake-up Input Type 11 27 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT12 Wake-up Input Type 12 28 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT13 Wake-up Input Type 13 29 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT14 Wake-up Input Type 14 30 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT15 Wake-up Input Type 15 31 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT2 Wake-up Input Type 2 18 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT3 Wake-up Input Type 3 19 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT4 Wake-up Input Type 4 20 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT5 Wake-up Input Type 5 21 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT6 Wake-up Input Type 6 22 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT7 Wake-up Input Type 7 23 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT8 Wake-up Input Type 8 24 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT9 Wake-up Input Type 9 25 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WUMR Supply Controller Wake-up Mode Register 0xC 32 read-write n 0x0 0x0 FWUPDBC Force Wake-up Debouncer Period 8 3 read-write IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x0 3_SCLK FWUP shall be low for at least 3 SLCK periods 0x1 32_SCLK FWUP shall be low for at least 32 SLCK periods 0x2 512_SCLK FWUP shall be low for at least 512 SLCK periods 0x3 4096_SCLK FWUP shall be low for at least 4,096 SLCK periods 0x4 32768_SCLK FWUP shall be low for at least 32,768 SLCK periods 0x5 FWUPEN Force Wake-up Enable 0 1 read-write NOT_ENABLE the Force Wake-up pin has no wake-up effect. 0 ENABLE the Force Wake-up pin low forces the wake-up of the core power supply. 1 RTCEN Real Time Clock Wake-up Enable 3 1 read-write NOT_ENABLE the RTC alarm signal has no wake-up effect. 0 ENABLE the RTC alarm signal forces the wake-up of the core power supply. 1 RTTEN Real Time Timer Wake-up Enable 2 1 read-write NOT_ENABLE the RTT alarm signal has no wake-up effect. 0 ENABLE the RTT alarm signal forces the wake-up of the core power supply. 1 SMEN Supply Monitor Wake-up Enable 1 1 read-write NOT_ENABLE the supply monitor detection has no wake-up effect. 0 ENABLE the supply monitor detection forces the wake-up of the core power supply. 1 WKUPDBC Wake-up Inputs Debouncer Period 12 3 read-write IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x0 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 0x1 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 0x2 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 0x3 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 0x4 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods 0x5 TC0 Timer Counter 0 TC 0x0 0x0 0x50 registers n TC0 27 TC1 28 TC2 29 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write FILTER 19 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TIOA2 Signal connected to XC2: TIOA2 3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC1 Timer Counter 1 TC 0x0 0x0 0x50 registers n TC3 30 TC4 31 TC5 32 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write FILTER 19 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TIOA2 Signal connected to XC2: TIOA2 3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC2 Timer Counter 2 TC 0x0 0x0 0x50 registers n TC6 33 TC7 34 TC8 35 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write FILTER 19 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TIOA2 Signal connected to XC2: TIOA2 3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0 SET Set 1 CLEAR Clear 2 TOGGLE Toggle 3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0 XC0 XC0 1 XC1 XC1 2 XC2 XC2 3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0 TIMER_CLOCK2 Clock selected: TCLK2 1 TIMER_CLOCK3 Clock selected: TCLK3 2 TIMER_CLOCK4 Clock selected: TCLK4 3 TIMER_CLOCK5 Clock selected: TCLK5 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 1 UP_RC UP mode with automatic trigger on RC Compare 2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TRNG True Random Number Generator TRNG 0x0 0x0 0x50 registers n TRNG 41 CR Control Register 0x0 32 write-only n 0x0 0x0 ENABLE Enables the TRNG to provide random values 0 1 write-only KEY Security Key 8 24 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready 0 1 read-only ODATA Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only TWI0 Two-wire Interface 0 TWI 0x0 0x0 0x50 registers n TWI0 22 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only QUICK SMBUS Quick Command 6 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (clear on read) 9 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only GACC General Call Access (clear on read) 5 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only RXBUFF RX Buffer Full 14 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only TXBUFE TX Buffer Empty 15 1 read-only TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TWI1 Two-wire Interface 1 TWI 0x0 0x0 0x50 registers n TWI1 23 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only QUICK SMBUS Quick Command 6 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (clear on read) 9 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only GACC General Call Access (clear on read) 5 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only RXBUFF RX Buffer Full 14 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only TXBUFE TX Buffer Empty 15 1 read-only TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write UART Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0x128 registers n UART 8 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 ENDRX Disable End of Receive Transfer Interrupt 3 1 write-only ENDTX Disable End of Transmit Interrupt 4 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXBUFF Disable Buffer Full Interrupt 12 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXBUFE Disable Buffer Empty Interrupt 11 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 ENDRX Enable End of Receive Transfer Interrupt 3 1 write-only ENDTX Enable End of Transmit Interrupt 4 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXBUFF Enable Buffer Full Interrupt 12 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXBUFE Enable Buffer Empty Interrupt 11 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 ENDRX Mask End of Receive Transfer Interrupt 3 1 read-only ENDTX Mask End of Transmit Interrupt 4 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXBUFF Mask RXBUFF Interrupt 12 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXBUFE Mask TXBUFE Interrupt 11 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo 0x1 LOCAL_LOOPBACK Local Loopback 0x2 REMOTE_LOOPBACK Remote Loopback 0x3 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No Parity 0x4 PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SR Status Register 0x14 32 read-only n 0x0 0x0 ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF Receive Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write UOTGHS USB On-The-Go Interface UOTGHS 0x0 0x0 0x50 registers n UOTGHS 40 CTRL General Control Register 0x800 32 read-write n 0x0 0x0 BCERRE B-Connection Error Interrupt Enable 4 1 read-write FRZCLK Freeze USB Clock 14 1 read-write HNPERRE HNP Error Interrupt Enable 6 1 read-write HNPREQ HNP Request 11 1 read-write IDTE ID Transition Interrupt Enable 0 1 read-write OTGPADE OTG Pad Enable 12 1 read-write ROLEEXE Role Exchange Interrupt Enable 5 1 read-write SRPE SRP Interrupt Enable 2 1 read-write SRPREQ SRP Request 10 1 read-write SRPSEL SRP Selection 9 1 read-write STOE Suspend Time-Out Interrupt Enable 7 1 read-write TIMPAGE Timer Page 20 2 read-write TIMVALUE Timer Value 16 2 read-write UIDE UOTGID Pin Enable 24 1 read-write UIMOD The USB mode (device/host) is selected from the UIMOD bit. 0 UOTGID The USB mode (device/host) is selected from the UOTGID input pin. 1 UIMOD UOTGHS Mode 25 1 read-write HOST The module is in USB host mode. 0 DEVICE The module is in USB device mode. 1 UNLOCK Timer Access Unlock 22 1 read-write USBE UOTGHS Enable 15 1 read-write VBERRE VBus Error Interrupt Enable 3 1 read-write VBUSHWC VBus Hardware Control 8 1 read-write VBUSPO VBus Polarity Off 13 1 read-write VBUSTE VBus Transition Interrupt Enable 1 1 read-write DEVCTRL Device General Control Register 0x0 32 read-write n 0x0 0x0 ADDEN Address Enable 7 1 read-write DETACH Detach 8 1 read-write LS Low-Speed Mode Force 12 1 read-write OPMODE2 Specific Operational mode 16 1 read-write RMWKUP Remote Wake-Up 9 1 read-write SPDCONF Mode Configuration 10 2 read-write NORMAL The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. 0x0 LOW_POWER For a better consumption, if high-speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The peripheral remains in full-speed mode whatever the host speed capability. 0x3 TSTJ Test mode J 13 1 read-write TSTK Test mode K 14 1 read-write TSTPCKT Test packet mode 15 1 read-write UADD USB Address 0 7 read-write DEVDMAADDRESS1 Device DMA Channel Address Register (n = 1) 0x314 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS2 Device DMA Channel Address Register (n = 2) 0x324 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS3 Device DMA Channel Address Register (n = 3) 0x334 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS4 Device DMA Channel Address Register (n = 4) 0x344 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS5 Device DMA Channel Address Register (n = 5) 0x354 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS6 Device DMA Channel Address Register (n = 6) 0x364 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS7 Device DMA Channel Address Register (n = 7) 0x374 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL1 Device DMA Channel Control Register (n = 1) 0x318 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL2 Device DMA Channel Control Register (n = 2) 0x328 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL3 Device DMA Channel Control Register (n = 3) 0x338 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL4 Device DMA Channel Control Register (n = 4) 0x348 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL5 Device DMA Channel Control Register (n = 5) 0x358 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL6 Device DMA Channel Control Register (n = 6) 0x368 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL7 Device DMA Channel Control Register (n = 7) 0x378 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMANXTDSC1 Device DMA Channel Next Descriptor Address Register (n = 1) 0x310 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC2 Device DMA Channel Next Descriptor Address Register (n = 2) 0x320 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC3 Device DMA Channel Next Descriptor Address Register (n = 3) 0x330 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC4 Device DMA Channel Next Descriptor Address Register (n = 4) 0x340 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC5 Device DMA Channel Next Descriptor Address Register (n = 5) 0x350 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC6 Device DMA Channel Next Descriptor Address Register (n = 6) 0x360 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC7 Device DMA Channel Next Descriptor Address Register (n = 7) 0x370 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMASTATUS1 Device DMA Channel Status Register (n = 1) 0x31C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS2 Device DMA Channel Status Register (n = 2) 0x32C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS3 Device DMA Channel Status Register (n = 3) 0x33C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS4 Device DMA Channel Status Register (n = 4) 0x34C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS5 Device DMA Channel Status Register (n = 5) 0x35C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS6 Device DMA Channel Status Register (n = 6) 0x36C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS7 Device DMA Channel Status Register (n = 7) 0x37C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVEPT Device Endpoint Register 0x1C 32 read-write n 0x0 0x0 EPEN0 Endpoint 0 Enable 0 1 read-write EPEN1 Endpoint 1 Enable 1 1 read-write EPEN2 Endpoint 2 Enable 2 1 read-write EPEN3 Endpoint 3 Enable 3 1 read-write EPEN4 Endpoint 4 Enable 4 1 read-write EPEN5 Endpoint 5 Enable 5 1 read-write EPEN6 Endpoint 6 Enable 6 1 read-write EPEN7 Endpoint 7 Enable 7 1 read-write EPEN8 Endpoint 8 Enable 8 1 read-write EPRST0 Endpoint 0 Reset 16 1 read-write EPRST1 Endpoint 1 Reset 17 1 read-write EPRST2 Endpoint 2 Reset 18 1 read-write EPRST3 Endpoint 3 Reset 19 1 read-write EPRST4 Endpoint 4 Reset 20 1 read-write EPRST5 Endpoint 5 Reset 21 1 read-write EPRST6 Endpoint 6 Reset 22 1 read-write EPRST7 Endpoint 7 Reset 23 1 read-write EPRST8 Endpoint 8 Reset 24 1 read-write DEVEPTCFG0 Device Endpoint Configuration Register (n = 0) 0x100 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG1 Device Endpoint Configuration Register (n = 0) 0x104 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG2 Device Endpoint Configuration Register (n = 0) 0x108 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG3 Device Endpoint Configuration Register (n = 0) 0x10C 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG4 Device Endpoint Configuration Register (n = 0) 0x110 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG5 Device Endpoint Configuration Register (n = 0) 0x114 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG6 Device Endpoint Configuration Register (n = 0) 0x118 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG7 Device Endpoint Configuration Register (n = 0) 0x11C 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG8 Device Endpoint Configuration Register (n = 0) 0x120 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG9 Device Endpoint Configuration Register (n = 0) 0x124 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[0] Device Endpoint Configuration Register (n = 0) 0x200 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[1] Device Endpoint Configuration Register (n = 0) 0x304 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[2] Device Endpoint Configuration Register (n = 0) 0x40C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[3] Device Endpoint Configuration Register (n = 0) 0x518 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[4] Device Endpoint Configuration Register (n = 0) 0x628 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[5] Device Endpoint Configuration Register (n = 0) 0x73C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[6] Device Endpoint Configuration Register (n = 0) 0x854 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[7] Device Endpoint Configuration Register (n = 0) 0x970 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[8] Device Endpoint Configuration Register (n = 0) 0xA90 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[9] Device Endpoint Configuration Register (n = 0) 0xBB4 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 DEVEPTICR0 Device Endpoint Clear Register (n = 0) 0x160 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR0_ISOENPT Device Endpoint Clear Register (n = 0) ISOENPT 0x160 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 write-only HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only HBISOINERRIC High bandwidth isochronous IN Underflow Error Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only DEVEPTICR1 Device Endpoint Clear Register (n = 0) 0x164 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR2 Device Endpoint Clear Register (n = 0) 0x168 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR3 Device Endpoint Clear Register (n = 0) 0x16C 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR4 Device Endpoint Clear Register (n = 0) 0x170 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR5 Device Endpoint Clear Register (n = 0) 0x174 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR6 Device Endpoint Clear Register (n = 0) 0x178 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR7 Device Endpoint Clear Register (n = 0) 0x17C 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR8 Device Endpoint Clear Register (n = 0) 0x180 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR9 Device Endpoint Clear Register (n = 0) 0x184 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[0] Device Endpoint Clear Register (n = 0) 0x2C0 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[1] Device Endpoint Clear Register (n = 0) 0x424 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[2] Device Endpoint Clear Register (n = 0) 0x58C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[3] Device Endpoint Clear Register (n = 0) 0x6F8 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[4] Device Endpoint Clear Register (n = 0) 0x868 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[5] Device Endpoint Clear Register (n = 0) 0x9DC 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[6] Device Endpoint Clear Register (n = 0) 0xB54 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[7] Device Endpoint Clear Register (n = 0) 0xCD0 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[8] Device Endpoint Clear Register (n = 0) 0xE50 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[9] Device Endpoint Clear Register (n = 0) 0xFD4 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTIDR0 Device Endpoint Disable Register (n = 0) 0x220 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR0_ISOENPT Device Endpoint Disable Register (n = 0) ISOENPT 0x220 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Clear 6 1 write-only DATAXEC DataX Interrupt Clear 9 1 write-only EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only ERRORTRANSEC Transaction Error Interrupt Clear 10 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only HBISOINERREC High Bandwidth Isochronous IN Error Interrupt Clear 3 1 write-only MDATEC MData Interrupt Clear 8 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only UNDERFEC Underflow Interrupt Clear 2 1 write-only DEVEPTIDR1 Device Endpoint Disable Register (n = 0) 0x224 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR2 Device Endpoint Disable Register (n = 0) 0x228 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR3 Device Endpoint Disable Register (n = 0) 0x22C 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR4 Device Endpoint Disable Register (n = 0) 0x230 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR5 Device Endpoint Disable Register (n = 0) 0x234 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR6 Device Endpoint Disable Register (n = 0) 0x238 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR7 Device Endpoint Disable Register (n = 0) 0x23C 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR8 Device Endpoint Disable Register (n = 0) 0x240 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR9 Device Endpoint Disable Register (n = 0) 0x244 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[0] Device Endpoint Disable Register (n = 0) 0x440 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[1] Device Endpoint Disable Register (n = 0) 0x664 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[2] Device Endpoint Disable Register (n = 0) 0x88C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[3] Device Endpoint Disable Register (n = 0) 0xAB8 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[4] Device Endpoint Disable Register (n = 0) 0xCE8 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[5] Device Endpoint Disable Register (n = 0) 0xF1C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[6] Device Endpoint Disable Register (n = 0) 0x1154 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[7] Device Endpoint Disable Register (n = 0) 0x1390 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[8] Device Endpoint Disable Register (n = 0) 0x15D0 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[9] Device Endpoint Disable Register (n = 0) 0x1814 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIER0 Device Endpoint Enable Register (n = 0) 0x1F0 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER0_ISOENPT Device Endpoint Enable Register (n = 0) ISOENPT 0x1F0 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 write-only DATAXES DataX Interrupt Enable 9 1 write-only EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only ERRORTRANSES Transaction Error Interrupt Enable 10 1 write-only FIFOCONS FIFO Control 14 1 write-only HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 write-only HBISOINERRES High Bandwidth Isochronous IN Error Interrupt Enable 3 1 write-only KILLBKS Kill IN Bank 13 1 write-only MDATAES MData Interrupt Enable 8 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only UNDERFES Underflow Interrupt Enable 2 1 write-only DEVEPTIER1 Device Endpoint Enable Register (n = 0) 0x1F4 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER2 Device Endpoint Enable Register (n = 0) 0x1F8 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER3 Device Endpoint Enable Register (n = 0) 0x1FC 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER4 Device Endpoint Enable Register (n = 0) 0x200 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER5 Device Endpoint Enable Register (n = 0) 0x204 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER6 Device Endpoint Enable Register (n = 0) 0x208 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER7 Device Endpoint Enable Register (n = 0) 0x20C 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER8 Device Endpoint Enable Register (n = 0) 0x210 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER9 Device Endpoint Enable Register (n = 0) 0x214 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[0] Device Endpoint Enable Register (n = 0) 0x3E0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[1] Device Endpoint Enable Register (n = 0) 0x5D4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[2] Device Endpoint Enable Register (n = 0) 0x7CC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[3] Device Endpoint Enable Register (n = 0) 0x9C8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[4] Device Endpoint Enable Register (n = 0) 0xBC8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[5] Device Endpoint Enable Register (n = 0) 0xDCC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[6] Device Endpoint Enable Register (n = 0) 0xFD4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[7] Device Endpoint Enable Register (n = 0) 0x11E0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[8] Device Endpoint Enable Register (n = 0) 0x13F0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[9] Device Endpoint Enable Register (n = 0) 0x1604 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIFR0 Device Endpoint Set Register (n = 0) 0x190 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR0_ISOENPT Device Endpoint Set Register (n = 0) ISOENPT 0x190 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 write-only HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 write-only HBISOINERRIS High bandwidth isochronous IN Underflow Error Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only DEVEPTIFR1 Device Endpoint Set Register (n = 0) 0x194 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR2 Device Endpoint Set Register (n = 0) 0x198 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR3 Device Endpoint Set Register (n = 0) 0x19C 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR4 Device Endpoint Set Register (n = 0) 0x1A0 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR5 Device Endpoint Set Register (n = 0) 0x1A4 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR6 Device Endpoint Set Register (n = 0) 0x1A8 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR7 Device Endpoint Set Register (n = 0) 0x1AC 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR8 Device Endpoint Set Register (n = 0) 0x1B0 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR9 Device Endpoint Set Register (n = 0) 0x1B4 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[0] Device Endpoint Set Register (n = 0) 0x320 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[1] Device Endpoint Set Register (n = 0) 0x4B4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[2] Device Endpoint Set Register (n = 0) 0x64C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[3] Device Endpoint Set Register (n = 0) 0x7E8 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[4] Device Endpoint Set Register (n = 0) 0x988 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[5] Device Endpoint Set Register (n = 0) 0xB2C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[6] Device Endpoint Set Register (n = 0) 0xCD4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[7] Device Endpoint Set Register (n = 0) 0xE80 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[8] Device Endpoint Set Register (n = 0) 0x1030 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[9] Device Endpoint Set Register (n = 0) 0x11E4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIMR0 Device Endpoint Mask Register (n = 0) 0x1C0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR0_ISOENPT Device Endpoint Mask Register (n = 0) ISOENPT 0x1C0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 read-only DATAXE DataX Interrupt 9 1 read-only EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only ERRORTRANSE Transaction Error Interrupt 10 1 read-only FIFOCON FIFO Control 14 1 read-only HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only HBISOINERRE High Bandwidth Isochronous IN Error Interrupt 3 1 read-only KILLBK Kill IN Bank 13 1 read-only MDATAE MData Interrupt 8 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only UNDERFE Underflow Interrupt 2 1 read-only DEVEPTIMR1 Device Endpoint Mask Register (n = 0) 0x1C4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR2 Device Endpoint Mask Register (n = 0) 0x1C8 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR3 Device Endpoint Mask Register (n = 0) 0x1CC 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR4 Device Endpoint Mask Register (n = 0) 0x1D0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR5 Device Endpoint Mask Register (n = 0) 0x1D4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR6 Device Endpoint Mask Register (n = 0) 0x1D8 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR7 Device Endpoint Mask Register (n = 0) 0x1DC 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR8 Device Endpoint Mask Register (n = 0) 0x1E0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR9 Device Endpoint Mask Register (n = 0) 0x1E4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[0] Device Endpoint Mask Register (n = 0) 0x380 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[1] Device Endpoint Mask Register (n = 0) 0x544 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[2] Device Endpoint Mask Register (n = 0) 0x70C 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[3] Device Endpoint Mask Register (n = 0) 0x8D8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[4] Device Endpoint Mask Register (n = 0) 0xAA8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[5] Device Endpoint Mask Register (n = 0) 0xC7C 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[6] Device Endpoint Mask Register (n = 0) 0xE54 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[7] Device Endpoint Mask Register (n = 0) 0x1030 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[8] Device Endpoint Mask Register (n = 0) 0x1210 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[9] Device Endpoint Mask Register (n = 0) 0x13F4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR0 Device Endpoint Status Register (n = 0) 0x130 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR0_ISOENPT Device Endpoint Status Register (n = 0) ISOENPT 0x130 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint) 0x2 MDATA MData toggle sequence (for high-bandwidth isochronous endpoint) 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 read-only HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UNDERFI Underflow Interrupt 2 1 read-only DEVEPTISR1 Device Endpoint Status Register (n = 0) 0x134 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR2 Device Endpoint Status Register (n = 0) 0x138 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR3 Device Endpoint Status Register (n = 0) 0x13C 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR4 Device Endpoint Status Register (n = 0) 0x140 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR5 Device Endpoint Status Register (n = 0) 0x144 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR6 Device Endpoint Status Register (n = 0) 0x148 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR7 Device Endpoint Status Register (n = 0) 0x14C 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR8 Device Endpoint Status Register (n = 0) 0x150 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR9 Device Endpoint Status Register (n = 0) 0x154 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[0] Device Endpoint Status Register (n = 0) 0x260 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[1] Device Endpoint Status Register (n = 0) 0x394 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[2] Device Endpoint Status Register (n = 0) 0x4CC 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[3] Device Endpoint Status Register (n = 0) 0x608 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[4] Device Endpoint Status Register (n = 0) 0x748 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[5] Device Endpoint Status Register (n = 0) 0x88C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[6] Device Endpoint Status Register (n = 0) 0x9D4 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[7] Device Endpoint Status Register (n = 0) 0xB20 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[8] Device Endpoint Status Register (n = 0) 0xC70 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[9] Device Endpoint Status Register (n = 0) 0xDC4 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read-write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVFNUM Device Frame Number Register 0x20 32 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only DEVICR Device Global Interrupt Clear Register 0x8 32 write-only n 0x0 0x0 EORSMC End of Resume Interrupt Clear 5 1 write-only EORSTC End of Reset Interrupt Clear 3 1 write-only MSOFC Micro Start of Frame Interrupt Clear 1 1 write-only SOFC Start of Frame Interrupt Clear 2 1 write-only SUSPC Suspend Interrupt Clear 0 1 write-only UPRSMC Upstream Resume Interrupt Clear 6 1 write-only WAKEUPC Wake-Up Interrupt Clear 4 1 write-only DEVIDR Device Global Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Disable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Disable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Disable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Disable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Disable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Disable 30 1 write-only EORSMEC End of Resume Interrupt Disable 5 1 write-only EORSTEC End of Reset Interrupt Disable 3 1 write-only MSOFEC Micro Start of Frame Interrupt Disable 1 1 write-only PEP_0 Endpoint 0 Interrupt Disable 12 1 write-only PEP_1 Endpoint 1 Interrupt Disable 13 1 write-only PEP_2 Endpoint 2 Interrupt Disable 14 1 write-only PEP_3 Endpoint 3 Interrupt Disable 15 1 write-only PEP_4 Endpoint 4 Interrupt Disable 16 1 write-only PEP_5 Endpoint 5 Interrupt Disable 17 1 write-only PEP_6 Endpoint 6 Interrupt Disable 18 1 write-only PEP_7 Endpoint 7 Interrupt Disable 19 1 write-only PEP_8 Endpoint 8 Interrupt Disable 20 1 write-only PEP_9 Endpoint 9 Interrupt Disable 21 1 write-only SOFEC Start of Frame Interrupt Disable 2 1 write-only SUSPEC Suspend Interrupt Disable 0 1 write-only UPRSMEC Upstream Resume Interrupt Disable 6 1 write-only WAKEUPEC Wake-Up Interrupt Disable 4 1 write-only DEVIER Device Global Interrupt Enable Register 0x18 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Enable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 write-only EORSMES End of Resume Interrupt Enable 5 1 write-only EORSTES End of Reset Interrupt Enable 3 1 write-only MSOFES Micro Start of Frame Interrupt Enable 1 1 write-only PEP_0 Endpoint 0 Interrupt Enable 12 1 write-only PEP_1 Endpoint 1 Interrupt Enable 13 1 write-only PEP_2 Endpoint 2 Interrupt Enable 14 1 write-only PEP_3 Endpoint 3 Interrupt Enable 15 1 write-only PEP_4 Endpoint 4 Interrupt Enable 16 1 write-only PEP_5 Endpoint 5 Interrupt Enable 17 1 write-only PEP_6 Endpoint 6 Interrupt Enable 18 1 write-only PEP_7 Endpoint 7 Interrupt Enable 19 1 write-only PEP_8 Endpoint 8 Interrupt Enable 20 1 write-only PEP_9 Endpoint 9 Interrupt Enable 21 1 write-only SOFES Start of Frame Interrupt Enable 2 1 write-only SUSPES Suspend Interrupt Enable 0 1 write-only UPRSMES Upstream Resume Interrupt Enable 6 1 write-only WAKEUPES Wake-Up Interrupt Enable 4 1 write-only DEVIFR Device Global Interrupt Set Register 0xC 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Set 25 1 write-only DMA_2 DMA Channel 2 Interrupt Set 26 1 write-only DMA_3 DMA Channel 3 Interrupt Set 27 1 write-only DMA_4 DMA Channel 4 Interrupt Set 28 1 write-only DMA_5 DMA Channel 5 Interrupt Set 29 1 write-only DMA_6 DMA Channel 6 Interrupt Set 30 1 write-only EORSMS End of Resume Interrupt Set 5 1 write-only EORSTS End of Reset Interrupt Set 3 1 write-only MSOFS Micro Start of Frame Interrupt Set 1 1 write-only SOFS Start of Frame Interrupt Set 2 1 write-only SUSPS Suspend Interrupt Set 0 1 write-only UPRSMS Upstream Resume Interrupt Set 6 1 write-only WAKEUPS Wake-Up Interrupt Set 4 1 write-only DEVIMR Device Global Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Mask 25 1 read-only DMA_2 DMA Channel 2 Interrupt Mask 26 1 read-only DMA_3 DMA Channel 3 Interrupt Mask 27 1 read-only DMA_4 DMA Channel 4 Interrupt Mask 28 1 read-only DMA_5 DMA Channel 5 Interrupt Mask 29 1 read-only DMA_6 DMA Channel 6 Interrupt Mask 30 1 read-only EORSME End of Resume Interrupt Mask 5 1 read-only EORSTE End of Reset Interrupt Mask 3 1 read-only MSOFE Micro Start of Frame Interrupt Mask 1 1 read-only PEP_0 Endpoint 0 Interrupt Mask 12 1 read-only PEP_1 Endpoint 1 Interrupt Mask 13 1 read-only PEP_2 Endpoint 2 Interrupt Mask 14 1 read-only PEP_3 Endpoint 3 Interrupt Mask 15 1 read-only PEP_4 Endpoint 4 Interrupt Mask 16 1 read-only PEP_5 Endpoint 5 Interrupt Mask 17 1 read-only PEP_6 Endpoint 6 Interrupt Mask 18 1 read-only PEP_7 Endpoint 7 Interrupt Mask 19 1 read-only PEP_8 Endpoint 8 Interrupt Mask 20 1 read-only PEP_9 Endpoint 9 Interrupt Mask 21 1 read-only SOFE Start of Frame Interrupt Mask 2 1 read-only SUSPE Suspend Interrupt Mask 0 1 read-only UPRSME Upstream Resume Interrupt Mask 6 1 read-only WAKEUPE Wake-Up Interrupt Mask 4 1 read-only DEVISR Device Global Interrupt Status Register 0x4 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only EORSM End of Resume Interrupt 5 1 read-only EORST End of Reset Interrupt 3 1 read-only MSOF Micro Start of Frame Interrupt 1 1 read-only PEP_0 Endpoint 0 Interrupt 12 1 read-only PEP_1 Endpoint 1 Interrupt 13 1 read-only PEP_2 Endpoint 2 Interrupt 14 1 read-only PEP_3 Endpoint 3 Interrupt 15 1 read-only PEP_4 Endpoint 4 Interrupt 16 1 read-only PEP_5 Endpoint 5 Interrupt 17 1 read-only PEP_6 Endpoint 6 Interrupt 18 1 read-only PEP_7 Endpoint 7 Interrupt 19 1 read-only PEP_8 Endpoint 8 Interrupt 20 1 read-only PEP_9 Endpoint 9 Interrupt 21 1 read-only SOF Start of Frame Interrupt 2 1 read-only SUSP Suspend Interrupt 0 1 read-only UPRSM Upstream Resume Interrupt 6 1 read-only WAKEUP Wake-Up Interrupt 4 1 read-only FSM General Finite State Machine Register 0x82C 32 read-only n 0x0 0x0 DRDSTATE Dual Role Device State 0 4 read-only A_IDLESTATE This is the start state for A-devices (when the ID pin is 0) 0x0 A_WAIT_VRISE In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). 0x1 A_WAIT_BCON In this state, the A-device waits for the B-device to signal a connection. 0x2 A_HOST In this state, the A-device that operates in Host mode is operational. 0x3 A_SUSPEND The A-device operating as a host is in the suspend mode. 0x4 A_PERIPHERAL The A-device operates as a peripheral. 0x5 A_WAIT_VFALL In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). 0x6 A_VBUS_ERR In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. 0x7 A_WAIT_DISCHARGE In this state, the A-device waits for the data USB line to discharge (100 us). 0x8 B_IDLE This is the start state for B-device (when the ID pin is 1). 0x9 B_PERIPHERAL In this state, the B-device acts as the peripheral. 0xA B_WAIT_BEGIN_HNP In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. 0xB B_WAIT_DISCHARGE In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. 0xC B_WAIT_ACON In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 0xD B_HOST In this state, the B-device acts as the Host. 0xE B_SRP_INIT In this state, the B-device attempts to start a session using the SRP protocol. 0xF HSTADDR1 Host Address 1 Register 0x424 32 read-write n 0x0 0x0 HSTADDRP0 USB Host Address 0 7 read-write HSTADDRP1 USB Host Address 8 7 read-write HSTADDRP2 USB Host Address 16 7 read-write HSTADDRP3 USB Host Address 24 7 read-write HSTADDR2 Host Address 2 Register 0x428 32 read-write n 0x0 0x0 HSTADDRP4 USB Host Address 0 7 read-write HSTADDRP5 USB Host Address 8 7 read-write HSTADDRP6 USB Host Address 16 7 read-write HSTADDRP7 USB Host Address 24 7 read-write HSTADDR3 Host Address 3 Register 0x42C 32 read-write n 0x0 0x0 HSTADDRP8 USB Host Address 0 7 read-write HSTADDRP9 USB Host Address 8 7 read-write HSTCTRL Host General Control Register 0x400 32 read-write n 0x0 0x0 RESET Send USB Reset 9 1 read-write RESUME Send USB Resume 10 1 read-write SOFE Start of Frame Generation Enable 8 1 read-write SPDCONF Mode Configuration 12 2 read-write NORMAL The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. 0x0 LOW_POWER For a better consumption, if high-speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The host remains to full-speed mode whatever the peripheral speed capability. 0x3 HSTDMAADDRESS1 Host DMA Channel Address Register (n = 1) 0x714 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS2 Host DMA Channel Address Register (n = 2) 0x724 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS3 Host DMA Channel Address Register (n = 3) 0x734 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS4 Host DMA Channel Address Register (n = 4) 0x744 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS5 Host DMA Channel Address Register (n = 5) 0x754 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS6 Host DMA Channel Address Register (n = 6) 0x764 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS7 Host DMA Channel Address Register (n = 7) 0x774 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL1 Host DMA Channel Control Register (n = 1) 0x718 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL2 Host DMA Channel Control Register (n = 2) 0x728 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL3 Host DMA Channel Control Register (n = 3) 0x738 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL4 Host DMA Channel Control Register (n = 4) 0x748 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL5 Host DMA Channel Control Register (n = 5) 0x758 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL6 Host DMA Channel Control Register (n = 6) 0x768 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL7 Host DMA Channel Control Register (n = 7) 0x778 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMANXTDSC1 Host DMA Channel Next Descriptor Address Register (n = 1) 0x710 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC2 Host DMA Channel Next Descriptor Address Register (n = 2) 0x720 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC3 Host DMA Channel Next Descriptor Address Register (n = 3) 0x730 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC4 Host DMA Channel Next Descriptor Address Register (n = 4) 0x740 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC5 Host DMA Channel Next Descriptor Address Register (n = 5) 0x750 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC6 Host DMA Channel Next Descriptor Address Register (n = 6) 0x760 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC7 Host DMA Channel Next Descriptor Address Register (n = 7) 0x770 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMASTATUS1 Host DMA Channel Status Register (n = 1) 0x71C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS2 Host DMA Channel Status Register (n = 2) 0x72C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS3 Host DMA Channel Status Register (n = 3) 0x73C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS4 Host DMA Channel Status Register (n = 4) 0x74C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS5 Host DMA Channel Status Register (n = 5) 0x75C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS6 Host DMA Channel Status Register (n = 6) 0x76C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS7 Host DMA Channel Status Register (n = 7) 0x77C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTFNUM Host Frame Number Register 0x420 32 read-write n 0x0 0x0 FLENHIGH Frame Length 16 8 read-write FNUM Frame Number 3 11 read-write MFNUM Micro Frame Number 0 3 read-write HSTICR Host Global Interrupt Clear Register 0x408 32 write-only n 0x0 0x0 DCONNIC Device Connection Interrupt Clear 0 1 write-only DDISCIC Device Disconnection Interrupt Clear 1 1 write-only HSOFIC Host Start of Frame Interrupt Clear 5 1 write-only HWUPIC Host Wake-Up Interrupt Clear 6 1 write-only RSMEDIC Downstream Resume Sent Interrupt Clear 3 1 write-only RSTIC USB Reset Sent Interrupt Clear 2 1 write-only RXRSMIC Upstream Resume Received Interrupt Clear 4 1 write-only HSTIDR Host Global Interrupt Disable Register 0x414 32 write-only n 0x0 0x0 DCONNIEC Device Connection Interrupt Disable 0 1 write-only DDISCIEC Device Disconnection Interrupt Disable 1 1 write-only DMA_1 DMA Channel 1 Interrupt Disable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Disable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Disable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Disable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Disable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Disable 30 1 write-only HSOFIEC Host Start of Frame Interrupt Disable 5 1 write-only HWUPIEC Host Wake-Up Interrupt Disable 6 1 write-only PEP_0 Pipe 0 Interrupt Disable 8 1 write-only PEP_1 Pipe 1 Interrupt Disable 9 1 write-only PEP_2 Pipe 2 Interrupt Disable 10 1 write-only PEP_3 Pipe 3 Interrupt Disable 11 1 write-only PEP_4 Pipe 4 Interrupt Disable 12 1 write-only PEP_5 Pipe 5 Interrupt Disable 13 1 write-only PEP_6 Pipe 6 Interrupt Disable 14 1 write-only PEP_7 Pipe 7 Interrupt Disable 15 1 write-only PEP_8 Pipe 8 Interrupt Disable 16 1 write-only PEP_9 Pipe 9 Interrupt Disable 17 1 write-only RSMEDIEC Downstream Resume Sent Interrupt Disable 3 1 write-only RSTIEC USB Reset Sent Interrupt Disable 2 1 write-only RXRSMIEC Upstream Resume Received Interrupt Disable 4 1 write-only HSTIER Host Global Interrupt Enable Register 0x418 32 write-only n 0x0 0x0 DCONNIES Device Connection Interrupt Enable 0 1 write-only DDISCIES Device Disconnection Interrupt Enable 1 1 write-only DMA_1 DMA Channel 1 Interrupt Enable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 write-only HSOFIES Host Start of Frame Interrupt Enable 5 1 write-only HWUPIES Host Wake-Up Interrupt Enable 6 1 write-only PEP_0 Pipe 0 Interrupt Enable 8 1 write-only PEP_1 Pipe 1 Interrupt Enable 9 1 write-only PEP_2 Pipe 2 Interrupt Enable 10 1 write-only PEP_3 Pipe 3 Interrupt Enable 11 1 write-only PEP_4 Pipe 4 Interrupt Enable 12 1 write-only PEP_5 Pipe 5 Interrupt Enable 13 1 write-only PEP_6 Pipe 6 Interrupt Enable 14 1 write-only PEP_7 Pipe 7 Interrupt Enable 15 1 write-only PEP_8 Pipe 8 Interrupt Enable 16 1 write-only PEP_9 Pipe 9 Interrupt Enable 17 1 write-only RSMEDIES Downstream Resume Sent Interrupt Enable 3 1 write-only RSTIES USB Reset Sent Interrupt Enable 2 1 write-only RXRSMIES Upstream Resume Received Interrupt Enable 4 1 write-only HSTIFR Host Global Interrupt Set Register 0x40C 32 write-only n 0x0 0x0 DCONNIS Device Connection Interrupt Set 0 1 write-only DDISCIS Device Disconnection Interrupt Set 1 1 write-only DMA_1 DMA Channel 1 Interrupt Set 25 1 write-only DMA_2 DMA Channel 2 Interrupt Set 26 1 write-only DMA_3 DMA Channel 3 Interrupt Set 27 1 write-only DMA_4 DMA Channel 4 Interrupt Set 28 1 write-only DMA_5 DMA Channel 5 Interrupt Set 29 1 write-only DMA_6 DMA Channel 6 Interrupt Set 30 1 write-only HSOFIS Host Start of Frame Interrupt Set 5 1 write-only HWUPIS Host Wake-Up Interrupt Set 6 1 write-only RSMEDIS Downstream Resume Sent Interrupt Set 3 1 write-only RSTIS USB Reset Sent Interrupt Set 2 1 write-only RXRSMIS Upstream Resume Received Interrupt Set 4 1 write-only HSTIMR Host Global Interrupt Mask Register 0x410 32 read-only n 0x0 0x0 DCONNIE Device Connection Interrupt Enable 0 1 read-only DDISCIE Device Disconnection Interrupt Enable 1 1 read-only DMA_1 DMA Channel 1 Interrupt Enable 25 1 read-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 read-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 read-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 read-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 read-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 read-only HSOFIE Host Start of Frame Interrupt Enable 5 1 read-only HWUPIE Host Wake-Up Interrupt Enable 6 1 read-only PEP_0 Pipe 0 Interrupt Enable 8 1 read-only PEP_1 Pipe 1 Interrupt Enable 9 1 read-only PEP_2 Pipe 2 Interrupt Enable 10 1 read-only PEP_3 Pipe 3 Interrupt Enable 11 1 read-only PEP_4 Pipe 4 Interrupt Enable 12 1 read-only PEP_5 Pipe 5 Interrupt Enable 13 1 read-only PEP_6 Pipe 6 Interrupt Enable 14 1 read-only PEP_7 Pipe 7 Interrupt Enable 15 1 read-only PEP_8 Pipe 8 Interrupt Enable 16 1 read-only PEP_9 Pipe 9 Interrupt Enable 17 1 read-only RSMEDIE Downstream Resume Sent Interrupt Enable 3 1 read-only RSTIE USB Reset Sent Interrupt Enable 2 1 read-only RXRSMIE Upstream Resume Received Interrupt Enable 4 1 read-only HSTISR Host Global Interrupt Status Register 0x404 32 read-only n 0x0 0x0 DCONNI Device Connection Interrupt 0 1 read-only DDISCI Device Disconnection Interrupt 1 1 read-only DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only HSOFI Host Start of Frame Interrupt 5 1 read-only HWUPI Host Wake-Up Interrupt 6 1 read-only PEP_0 Pipe 0 Interrupt 8 1 read-only PEP_1 Pipe 1 Interrupt 9 1 read-only PEP_2 Pipe 2 Interrupt 10 1 read-only PEP_3 Pipe 3 Interrupt 11 1 read-only PEP_4 Pipe 4 Interrupt 12 1 read-only PEP_5 Pipe 5 Interrupt 13 1 read-only PEP_6 Pipe 6 Interrupt 14 1 read-only PEP_7 Pipe 7 Interrupt 15 1 read-only PEP_8 Pipe 8 Interrupt 16 1 read-only PEP_9 Pipe 9 Interrupt 17 1 read-only RSMEDI Downstream Resume Sent Interrupt 3 1 read-only RSTI USB Reset Sent Interrupt 2 1 read-only RXRSMI Upstream Resume Received Interrupt 4 1 read-only HSTPIP Host Pipe Register 0x41C 32 read-write n 0x0 0x0 PEN0 Pipe 0 Enable 0 1 read-write PEN1 Pipe 1 Enable 1 1 read-write PEN2 Pipe 2 Enable 2 1 read-write PEN3 Pipe 3 Enable 3 1 read-write PEN4 Pipe 4 Enable 4 1 read-write PEN5 Pipe 5 Enable 5 1 read-write PEN6 Pipe 6 Enable 6 1 read-write PEN7 Pipe 7 Enable 7 1 read-write PEN8 Pipe 8 Enable 8 1 read-write PRST0 Pipe 0 Reset 16 1 read-write PRST1 Pipe 1 Reset 17 1 read-write PRST2 Pipe 2 Reset 18 1 read-write PRST3 Pipe 3 Reset 19 1 read-write PRST4 Pipe 4 Reset 20 1 read-write PRST5 Pipe 5 Reset 21 1 read-write PRST6 Pipe 6 Reset 22 1 read-write PRST7 Pipe 7 Reset 23 1 read-write PRST8 Pipe 8 Reset 24 1 read-write HSTPIPCFG0 Host Pipe Configuration Register (n = 0) 0x500 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG0_HSBOHSCP Host Pipe Configuration Register (n = 0) HSBOHSCP 0x500 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write BINTERVAL Binterval Parameter for the Bulk-Out/Ping Transaction 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PINGEN Ping Enable 20 1 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 BLK Bulk 0x2 HSTPIPCFG1 Host Pipe Configuration Register (n = 0) 0x504 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG2 Host Pipe Configuration Register (n = 0) 0x508 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG3 Host Pipe Configuration Register (n = 0) 0x50C 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG4 Host Pipe Configuration Register (n = 0) 0x510 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG5 Host Pipe Configuration Register (n = 0) 0x514 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG6 Host Pipe Configuration Register (n = 0) 0x518 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG7 Host Pipe Configuration Register (n = 0) 0x51C 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG8 Host Pipe Configuration Register (n = 0) 0x520 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG9 Host Pipe Configuration Register (n = 0) 0x524 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[0] Host Pipe Configuration Register (n = 0) 0xA00 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[1] Host Pipe Configuration Register (n = 0) 0xF04 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[2] Host Pipe Configuration Register (n = 0) 0x140C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[3] Host Pipe Configuration Register (n = 0) 0x1918 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[4] Host Pipe Configuration Register (n = 0) 0x1E28 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[5] Host Pipe Configuration Register (n = 0) 0x233C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[6] Host Pipe Configuration Register (n = 0) 0x2854 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[7] Host Pipe Configuration Register (n = 0) 0x2D70 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[8] Host Pipe Configuration Register (n = 0) 0x3290 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[9] Host Pipe Configuration Register (n = 0) 0x37B4 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPERR0 Host Pipe Error Register (n = 0) 0x680 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR1 Host Pipe Error Register (n = 0) 0x684 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR2 Host Pipe Error Register (n = 0) 0x688 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR3 Host Pipe Error Register (n = 0) 0x68C 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR4 Host Pipe Error Register (n = 0) 0x690 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR5 Host Pipe Error Register (n = 0) 0x694 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR6 Host Pipe Error Register (n = 0) 0x698 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR7 Host Pipe Error Register (n = 0) 0x69C 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR8 Host Pipe Error Register (n = 0) 0x6A0 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR9 Host Pipe Error Register (n = 0) 0x6A4 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[0] Host Pipe Error Register (n = 0) 0xD00 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[1] Host Pipe Error Register (n = 0) 0x1384 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[2] Host Pipe Error Register (n = 0) 0x1A0C 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[3] Host Pipe Error Register (n = 0) 0x2098 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[4] Host Pipe Error Register (n = 0) 0x2728 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[5] Host Pipe Error Register (n = 0) 0x2DBC 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[6] Host Pipe Error Register (n = 0) 0x3454 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[7] Host Pipe Error Register (n = 0) 0x3AF0 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[8] Host Pipe Error Register (n = 0) 0x4190 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[9] Host Pipe Error Register (n = 0) 0x4834 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPICR0 Host Pipe Clear Register (n = 0) 0x560 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR0_INTPIPES Host Pipe Clear Register (n = 0) INTPIPES 0x560 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only HSTPIPICR0_ISOPIPES Host Pipe Clear Register (n = 0) ISOPIPES 0x560 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 write-only NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only HSTPIPICR1 Host Pipe Clear Register (n = 0) 0x564 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR2 Host Pipe Clear Register (n = 0) 0x568 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR3 Host Pipe Clear Register (n = 0) 0x56C 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR4 Host Pipe Clear Register (n = 0) 0x570 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR5 Host Pipe Clear Register (n = 0) 0x574 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR6 Host Pipe Clear Register (n = 0) 0x578 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR7 Host Pipe Clear Register (n = 0) 0x57C 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR8 Host Pipe Clear Register (n = 0) 0x580 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR9 Host Pipe Clear Register (n = 0) 0x584 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[0] Host Pipe Clear Register (n = 0) 0xAC0 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[1] Host Pipe Clear Register (n = 0) 0x1024 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[2] Host Pipe Clear Register (n = 0) 0x158C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[3] Host Pipe Clear Register (n = 0) 0x1AF8 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[4] Host Pipe Clear Register (n = 0) 0x2068 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[5] Host Pipe Clear Register (n = 0) 0x25DC 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[6] Host Pipe Clear Register (n = 0) 0x2B54 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[7] Host Pipe Clear Register (n = 0) 0x30D0 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[8] Host Pipe Clear Register (n = 0) 0x3650 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[9] Host Pipe Clear Register (n = 0) 0x3BD4 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPIDR0 Host Pipe Disable Register (n = 0) 0x620 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR0_INTPIPES Host Pipe Disable Register (n = 0) INTPIPES 0x620 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only HSTPIPIDR0_ISOPIPES Host Pipe Disable Register (n = 0) ISOPIPES 0x620 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 write-only FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only HSTPIPIDR1 Host Pipe Disable Register (n = 0) 0x624 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR2 Host Pipe Disable Register (n = 0) 0x628 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR3 Host Pipe Disable Register (n = 0) 0x62C 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR4 Host Pipe Disable Register (n = 0) 0x630 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR5 Host Pipe Disable Register (n = 0) 0x634 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR6 Host Pipe Disable Register (n = 0) 0x638 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR7 Host Pipe Disable Register (n = 0) 0x63C 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR8 Host Pipe Disable Register (n = 0) 0x640 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR9 Host Pipe Disable Register (n = 0) 0x644 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[0] Host Pipe Disable Register (n = 0) 0xC40 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[1] Host Pipe Disable Register (n = 0) 0x1264 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[2] Host Pipe Disable Register (n = 0) 0x188C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[3] Host Pipe Disable Register (n = 0) 0x1EB8 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[4] Host Pipe Disable Register (n = 0) 0x24E8 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[5] Host Pipe Disable Register (n = 0) 0x2B1C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[6] Host Pipe Disable Register (n = 0) 0x3154 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[7] Host Pipe Disable Register (n = 0) 0x3790 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[8] Host Pipe Disable Register (n = 0) 0x3DD0 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[9] Host Pipe Disable Register (n = 0) 0x4414 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIER0 Host Pipe Enable Register (n = 0) 0x5F0 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER0_INTPIPES Host Pipe Enable Register (n = 0) INTPIPES 0x5F0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only HSTPIPIER0_ISOPIPES Host Pipe Enable Register (n = 0) ISOPIPES 0x5F0 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 write-only NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only HSTPIPIER1 Host Pipe Enable Register (n = 0) 0x5F4 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER2 Host Pipe Enable Register (n = 0) 0x5F8 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER3 Host Pipe Enable Register (n = 0) 0x5FC 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER4 Host Pipe Enable Register (n = 0) 0x600 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER5 Host Pipe Enable Register (n = 0) 0x604 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER6 Host Pipe Enable Register (n = 0) 0x608 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER7 Host Pipe Enable Register (n = 0) 0x60C 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER8 Host Pipe Enable Register (n = 0) 0x610 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER9 Host Pipe Enable Register (n = 0) 0x614 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[0] Host Pipe Enable Register (n = 0) 0xBE0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[1] Host Pipe Enable Register (n = 0) 0x11D4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[2] Host Pipe Enable Register (n = 0) 0x17CC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[3] Host Pipe Enable Register (n = 0) 0x1DC8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[4] Host Pipe Enable Register (n = 0) 0x23C8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[5] Host Pipe Enable Register (n = 0) 0x29CC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[6] Host Pipe Enable Register (n = 0) 0x2FD4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[7] Host Pipe Enable Register (n = 0) 0x35E0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[8] Host Pipe Enable Register (n = 0) 0x3BF0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[9] Host Pipe Enable Register (n = 0) 0x4204 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIFR0 Host Pipe Set Register (n = 0) 0x590 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR0_INTPIPES Host Pipe Set Register (n = 0) INTPIPES 0x590 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only HSTPIPIFR0_ISOPIPES Host Pipe Set Register (n = 0) ISOPIPES 0x590 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 write-only NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only HSTPIPIFR1 Host Pipe Set Register (n = 0) 0x594 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR2 Host Pipe Set Register (n = 0) 0x598 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR3 Host Pipe Set Register (n = 0) 0x59C 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR4 Host Pipe Set Register (n = 0) 0x5A0 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR5 Host Pipe Set Register (n = 0) 0x5A4 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR6 Host Pipe Set Register (n = 0) 0x5A8 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR7 Host Pipe Set Register (n = 0) 0x5AC 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR8 Host Pipe Set Register (n = 0) 0x5B0 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR9 Host Pipe Set Register (n = 0) 0x5B4 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[0] Host Pipe Set Register (n = 0) 0xB20 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[1] Host Pipe Set Register (n = 0) 0x10B4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[2] Host Pipe Set Register (n = 0) 0x164C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[3] Host Pipe Set Register (n = 0) 0x1BE8 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[4] Host Pipe Set Register (n = 0) 0x2188 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[5] Host Pipe Set Register (n = 0) 0x272C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[6] Host Pipe Set Register (n = 0) 0x2CD4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[7] Host Pipe Set Register (n = 0) 0x3280 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[8] Host Pipe Set Register (n = 0) 0x3830 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[9] Host Pipe Set Register (n = 0) 0x3DE4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIMR0 Host Pipe Mask Register (n = 0) 0x5C0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR0_INTPIPES Host Pipe Mask Register (n = 0) INTPIPES 0x5C0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only HSTPIPIMR0_ISOPIPES Host Pipe Mask Register (n = 0) ISOPIPES 0x5C0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 read-only FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only HSTPIPIMR1 Host Pipe Mask Register (n = 0) 0x5C4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR2 Host Pipe Mask Register (n = 0) 0x5C8 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR3 Host Pipe Mask Register (n = 0) 0x5CC 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR4 Host Pipe Mask Register (n = 0) 0x5D0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR5 Host Pipe Mask Register (n = 0) 0x5D4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR6 Host Pipe Mask Register (n = 0) 0x5D8 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR7 Host Pipe Mask Register (n = 0) 0x5DC 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR8 Host Pipe Mask Register (n = 0) 0x5E0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR9 Host Pipe Mask Register (n = 0) 0x5E4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[0] Host Pipe Mask Register (n = 0) 0xB80 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[1] Host Pipe Mask Register (n = 0) 0x1144 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[2] Host Pipe Mask Register (n = 0) 0x170C 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[3] Host Pipe Mask Register (n = 0) 0x1CD8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[4] Host Pipe Mask Register (n = 0) 0x22A8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[5] Host Pipe Mask Register (n = 0) 0x287C 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[6] Host Pipe Mask Register (n = 0) 0x2E54 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[7] Host Pipe Mask Register (n = 0) 0x3430 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[8] Host Pipe Mask Register (n = 0) 0x3A10 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[9] Host Pipe Mask Register (n = 0) 0x3FF4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPINRQ0 Host Pipe IN Request Register (n = 0) 0x650 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ1 Host Pipe IN Request Register (n = 0) 0x654 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ2 Host Pipe IN Request Register (n = 0) 0x658 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ3 Host Pipe IN Request Register (n = 0) 0x65C 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ4 Host Pipe IN Request Register (n = 0) 0x660 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ5 Host Pipe IN Request Register (n = 0) 0x664 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ6 Host Pipe IN Request Register (n = 0) 0x668 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ7 Host Pipe IN Request Register (n = 0) 0x66C 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ8 Host Pipe IN Request Register (n = 0) 0x670 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ9 Host Pipe IN Request Register (n = 0) 0x674 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[0] Host Pipe IN Request Register (n = 0) 0xCA0 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[1] Host Pipe IN Request Register (n = 0) 0x12F4 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[2] Host Pipe IN Request Register (n = 0) 0x194C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[3] Host Pipe IN Request Register (n = 0) 0x1FA8 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[4] Host Pipe IN Request Register (n = 0) 0x2608 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[5] Host Pipe IN Request Register (n = 0) 0x2C6C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[6] Host Pipe IN Request Register (n = 0) 0x32D4 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[7] Host Pipe IN Request Register (n = 0) 0x3940 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[8] Host Pipe IN Request Register (n = 0) 0x3FB0 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[9] Host Pipe IN Request Register (n = 0) 0x4624 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPISR0 Host Pipe Status Register (n = 0) 0x530 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR0_INTPIPES Host Pipe Status Register (n = 0) INTPIPES 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only HSTPIPISR0_ISOPIPES Host Pipe Status Register (n = 0) ISOPIPES 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only HSTPIPISR1 Host Pipe Status Register (n = 0) 0x534 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR2 Host Pipe Status Register (n = 0) 0x538 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR3 Host Pipe Status Register (n = 0) 0x53C 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR4 Host Pipe Status Register (n = 0) 0x540 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR5 Host Pipe Status Register (n = 0) 0x544 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR6 Host Pipe Status Register (n = 0) 0x548 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR7 Host Pipe Status Register (n = 0) 0x54C 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR8 Host Pipe Status Register (n = 0) 0x550 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR9 Host Pipe Status Register (n = 0) 0x554 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[0] Host Pipe Status Register (n = 0) 0xA60 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[1] Host Pipe Status Register (n = 0) 0xF94 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[2] Host Pipe Status Register (n = 0) 0x14CC 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[3] Host Pipe Status Register (n = 0) 0x1A08 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[4] Host Pipe Status Register (n = 0) 0x1F48 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[5] Host Pipe Status Register (n = 0) 0x248C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[6] Host Pipe Status Register (n = 0) 0x29D4 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[7] Host Pipe Status Register (n = 0) 0x2F20 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[8] Host Pipe Status Register (n = 0) 0x3470 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[9] Host Pipe Status Register (n = 0) 0x39C4 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read-write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only SCR General Status Clear Register 0x808 32 write-only n 0x0 0x0 BCERRIC B-Connection Error Interrupt Clear 4 1 write-only HNPERRIC HNP Error Interrupt Clear 6 1 write-only IDTIC ID Transition Interrupt Clear 0 1 write-only ROLEEXIC Role Exchange Interrupt Clear 5 1 write-only SRPIC SRP Interrupt Clear 2 1 write-only STOIC Suspend Time-Out Interrupt Clear 7 1 write-only VBERRIC VBus Error Interrupt Clear 3 1 write-only VBUSRQC VBus Request Clear 9 1 write-only VBUSTIC VBus Transition Interrupt Clear 1 1 write-only SFR General Status Set Register 0x80C 32 write-only n 0x0 0x0 BCERRIS B-Connection Error Interrupt Set 4 1 write-only HNPERRIS HNP Error Interrupt Set 6 1 write-only IDTIS ID Transition Interrupt Set 0 1 write-only ROLEEXIS Role Exchange Interrupt Set 5 1 write-only SRPIS SRP Interrupt Set 2 1 write-only STOIS Suspend Time-Out Interrupt Set 7 1 write-only VBERRIS VBus Error Interrupt Set 3 1 write-only VBUSRQS VBus Request Set 9 1 write-only VBUSTIS VBus Transition Interrupt Set 1 1 write-only SR General Status Register 0x804 32 read-only n 0x0 0x0 BCERRI B-Connection Error Interrupt 4 1 read-only CLKUSABLE UTMI Clock Usable 14 1 read-only HNPERRI HNP Error Interrupt 6 1 read-only ID UOTGID Pin State 10 1 read-only IDTI ID Transition Interrupt 0 1 read-only ROLEEXI Role Exchange Interrupt 5 1 read-only SPEED Speed Status 12 2 read-only FULL_SPEED Full-Speed mode 0x0 HIGH_SPEED High-Speed mode 0x1 LOW_SPEED Low-Speed mode 0x2 SRPI SRP Interrupt 2 1 read-only STOI Suspend Time-Out Interrupt 7 1 read-only VBERRI VBus Error Interrupt 3 1 read-only VBUS VBus Level 11 1 read-only VBUSRQ VBus Request 9 1 read-only VBUSTI VBus Transition Interrupt 1 1 read-only USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 USART 0x0 0x0 0x50 registers n USART0 17 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Rearm Time-out 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Disable 19 1 write-only RTSEN Request to Send Enable 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Start Time-out 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only MANERR Manchester Error 24 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBRK Break Received/End of Break 2 1 read-only RXBUFF Reception Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error 6 1 read-only LINBE LIN Bit Error 25 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only LINTC LIN Transfer Completed 15 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only UNRE Underrun Error 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM PDC Mode 16 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Infrared Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 USART 0x0 0x0 0x50 registers n USART1 18 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Rearm Time-out 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Disable 19 1 write-only RTSEN Request to Send Enable 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Start Time-out 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only MANERR Manchester Error 24 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBRK Break Received/End of Break 2 1 read-only RXBUFF Reception Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error 6 1 read-only LINBE LIN Bit Error 25 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only LINTC LIN Transfer Completed 15 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only UNRE Underrun Error 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM PDC Mode 16 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Infrared Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART2 Universal Synchronous Asynchronous Receiver Transmitter 2 USART 0x0 0x0 0x50 registers n USART2 19 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Rearm Time-out 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Disable 19 1 write-only RTSEN Request to Send Enable 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Start Time-out 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only MANERR Manchester Error 24 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBRK Break Received/End of Break 2 1 read-only RXBUFF Reception Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error 6 1 read-only LINBE LIN Bit Error 25 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only LINTC LIN Transfer Completed 15 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only UNRE Underrun Error 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM PDC Mode 16 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Infrared Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART3 Universal Synchronous Asynchronous Receiver Transmitter 3 USART 0x0 0x0 0x50 registers n USART3 20 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Rearm Time-out 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Disable 19 1 write-only RTSEN Request to Send Enable 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Start Time-out 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only MANERR Manchester Error 24 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBRK Break Received/End of Break 2 1 read-only RXBUFF Reception Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error 6 1 read-only LINBE LIN Bit Error 25 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only LINTC LIN Transfer Completed 15 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only UNRE Underrun Error 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM PDC Mode 16 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Infrared Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only WDT Watchdog Timer SYSC 0x0 0x0 0x10 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password. 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 WDRSTT Watchdog Restart 0 1 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 WDD Watchdog Delta Value 16 12 read-write WDDBGHLT Watchdog Debug Halt 28 1 read-write WDDIS Watchdog Disable 15 1 read-write WDFIEN Watchdog Fault Interrupt Enable 12 1 read-write WDIDLEHLT Watchdog Idle Halt 29 1 read-write WDRPROC Watchdog Reset Processor 14 1 read-write WDRSTEN Watchdog Reset Enable 13 1 read-write WDV Watchdog Counter Value 0 12 read-write SR Status Register 0x8 32 read-only n 0x0 0x0 WDERR Watchdog Error 1 1 read-only WDUNF Watchdog Underflow 0 1 read-only